How to describe a FMAC insn

How to describe a FMAC insn

[Qing Wei]

Hi,
Could someone give some hints of how to describe a FMAC (float mult and
add) insn in machine description, it matches d = b*c+a, which is a four
operands float instrution. With a glimp through the array optabs[] in
genopinit.c, it seems no OP handler could match FMAC operation? And I
found a function gen_add_mult() in loops.c, but it also seems not very
helpful. And another my question is, the element of optabs[] are arrays
indexed by machine code, for example, add_optab[] indexed by SI, DI, QI,
FI machine mode, not by number of operands, it seems it only matches 3
operands add operation,if I want to add a four operands add operation,
what should I do?

Qing

Re: How to describe a FMAC insn

[Tim Prince]

Qing Wei wrote:
> Could someone give some hints of how to describe a FMAC (float mult and
> add) insn in machine description, it matches d = b*c+a, which is a four
> operands float instrution. 
There are plenty of examples in ia64.md and rs6000.md.

Re: How to describe a FMAC insn

[Qing Wei]

I tried by referring the ia64.md, unfortunately it does not work. The
insn I wrote for FMAC is as follows,

(define_insn "maddsi4"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 3 "register_operand" "r")))]
""
"fma %0, %1, %2, %3")

And besides this, I defined other two insns for dedicated add and mult
operations as follows,

(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))
)]
""
"add %0, %1, %2")

(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))
)]
""
"mul %0, %1, %2")

It seems trivial. But after I rebuilt GCC for this new target, I found
that no optabs entry is initialized for maddsi4 in insn-opinit.c which
is generated by genopinit. However, the add_optab and smul_optab do be
initialized with Code_for_addsi3/mulsi3. As a result, when I test the
following simple program, cc1 produces separate add and mul instructions
rather than fma, where the problem is? Thanks.

void f(int s1[], int s2[], int s3[], int s4[])
{
int j;

for (j = 0; j < 16; j++)
s4[j] = s1[j]*s2[j]+s3[j];
}

Qing
>> Could someone give some hints of how to describe a FMAC (float mult and
>> add) insn in machine description, it matches d = b*c+a, which is a four
>> operands float instrution. 
>>     
> There are plenty of examples in ia64.md and rs6000.md.
>   

Re: How to describe a FMAC insn

[Rask Ingemann Lambertsen]

On Wed, Dec 26, 2007 at 06:59:39AM -0800, Qing Wei wrote:
> I tried by referring the ia64.md, unfortunately it does not work. The
> insn I wrote for FMAC is as follows,
> 
> (define_insn "maddsi4"
> [(set (match_operand:SI 0 "register_operand" "=r")
> (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
> (match_operand:SI 2 "register_operand" "r"))
> (match_operand:SI 3 "register_operand" "r")))]
> ""
> "fma %0, %1, %2, %3")
[...]
> It seems trivial. But after I rebuilt GCC for this new target, I found
> that no optabs entry is initialized for maddsi4 in insn-opinit.c which
> is generated by genopinit.

   It would be called maddhisi4, maddsidi4 or so for a sign-extending
instruction. If your instruction is a plain multiply-add instruction (which
is how you've defined it above), then there is no optab for it.

> However, the add_optab and smul_optab do be
> initialized with Code_for_addsi3/mulsi3. As a result, when I test the
> following simple program, cc1 produces separate add and mul instructions
> rather than fma, where the problem is? Thanks.

   Look at the dump file produced by -fdump-rtl-combine-details.

-- 
Rask Ingemann Lambertsen
Danish law requires addresses in e-mail to be logged and stored for a year

Re: How to describe a FMAC insn

[Richard Kenner]

> Could someone give some hints of how to describe a FMAC (float mult and
> add) insn in machine description, it matches d = b*c+a, which is a four
> operands float instrution. With a glimp through the array optabs[] in
> genopinit.c, it seems no OP handler could match FMAC operation? 

Correct.  It isn't generated directly during RTL generation, but instead
created by the optimizer (combine) from add and multiply insns.