Re: Invalid reload inheritance with paradoxical subregs

[Hans-Peter Nilsson <hp@bitrange.com>]

On Thu, 2 Apr 2009, Uros Bizjak wrote:
> Combine simplifies lshiftrt/shift/and combined instruction under the
> assumption, that for ZERO_EXTEND LOAD_EXTEND_OP targets it can prove
> that certain bits are zero, so AND operation can be omitted. The
> resulting instruction is valid only for memory operand:
...
> (gdb) p debug_rtx (insn)
> (insn 121 120 125 2 t.c:22 (set (reg:SI 6 r6 [orig:48 y$k.115 ] [48])
>         (lshiftrt:SI (subreg:SI (reg:HI 7 r7) 0)
>             (const_int 5 [0x5]))) 62 {lshrsi3} (nil))
>
> This substitution is wrong. Paradoxical subreg  of a memory operand is
> for our target known to zero extend to SImode value, however -
> paradoxical subreg of a register operand has undefined bits outside
> the reg. So, combine and reload doesn't agree on the bits outside the
> register.

Looks like the issue I attributed to IRA for
mmix-knuth-mmixware:
<http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38603>
(no, not a great deal of analysis there, I'm afraid).

And again, I'd be perfectly fine with removing this weird
LOAD_EXTEND_OP-specific "feature".  I'm of half a mind to remove
the #define from the MMIX port.

brgds, H-P