From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20635 invoked by alias); 24 Jun 2009 08:56:33 -0000 Received: (qmail 20625 invoked by uid 22791); 24 Jun 2009 08:56:31 -0000 X-SWARE-Spam-Status: No, hits=1.1 required=5.0 tests=AWL,BAYES_50,J_CHICKENPOX_43 X-Spam-Check-By: sourceware.org Received: from 178.200.DSNET (HELO mail.mavrixtech.com.cn) (203.110.178.200) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 24 Jun 2009 08:56:21 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mavrixtech.com.cn (Postfix) with ESMTP id 7A69D50C9E1B; Wed, 24 Jun 2009 16:54:01 +0800 (CST) Received: from mail.mavrixtech.com.cn ([127.0.0.1]) by localhost (mail.mavrixtech.com.cn [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id y0lxm3iJpoit; Wed, 24 Jun 2009 16:54:00 +0800 (CST) Received: from danielshmr (daniel-shmr.actions.com.cn [192.168.95.243]) by mail.mavrixtech.com.cn (Postfix) with ESMTP id DBE5250C9E1A; Wed, 24 Jun 2009 16:54:00 +0800 (CST) From: "daniel.tian" To: "'Paolo Bonzini'" Cc: , "'Peng Zheng'" Subject: re: How to deal with unrecognizable RTL code Date: Wed, 24 Jun 2009 09:35:00 -0000 MIME-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable In-Reply-To: <4A3B7CD9.4030702@gnu.org> Message-Id: <20090624085400.DBE5250C9E1A@mail.mavrixtech.com.cn> Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2009-06/txt/msg00557.txt.bz2 Hi: >> 1) does your machine use cc0? No. In my RISC chip, there is a status register existed, like ARM. But I now I didn't write any code to support it, as well as absent cc0 register. =20 >> 2) what pass is producing those subregs? This is really puzzled me. I just wrote the PROMOTE_MODE like MIPS.=20 >> 3) what is your definition of GO_IF_LEGITIMATE_ADDRESS? Here is my definition of GO_IF_LEGITIMATE_ADDRESS: #ifndef REG_OK_STRICT #define RICE_REG_STRICT_P 0 #else /* REG_OK_STRICT */ #define RICE_REG_STRICT_P 1 #endif /* REG_OK_STRICT */ #define GO_IF_LEGITIMATE_ADDRESS(mode,x,label) \ {\ if (rice_go_if_legitimate_address(mode, x, RICE_REG_STRICT_P))\ goto label;\ } int rice_go_if_legitimate_address(enum machine_mode mode,rtx X, int bIsStrict) { rtx op1,op2; enum rtx_code code =3D GET_CODE (X); =09 //(Rmem) #4/2/1 -PRI/PRD/POI/POD=09 if ((code =3D=3D PRE_INC || code =3D=3D PRE_DEC) && (GET_MODE_SIZE (mode) <=3D 4)) { rtx op1; op1=3DXEXP(X, 0); if(GET_CODE(op1) =3D=3D REG) return is_base_reg_strict(REGNO(op1)); else=20 return RICE_NO; } //(Rmem) {Rx, #UImm8} -PRI/PRD/POI/POD -W if ((code =3D=3D POST_MODIFY || code =3D=3D PRE_MODIFY) && rice_reg_ok_for_base (XEXP (X, 0), bIsStrict) && GET_CODE (XEXP (X, 1)) =3D=3D PLUS && rtx_equal_p (XEXP (XEXP (X, 1), 0), XEXP (X, 0))) { rtx addend =3D XEXP (XEXP (X, 1), 1); return (rice_if_legitimate_index (mode, addend, bIsStrict)); } =09 if(GET_CODE(X) =3D=3D PLUS) { //check where the form is like (Rmem) {Rx, #UImm8} return rice_base_index_address(X, bIsStrict);=20 } return RICE_NO; } BTY: the address mode in my RISC chip is like the following: LOADW Rd (Rs) Rx/offset(8bits unsigned immediate)=20 Which means Rd =3D (Rs + Rx) 0r Rd =3D (Rs + imm_8bits). So if the immediate offset is larger than 255, it should be move into register first. I think this definition in my port is appropriate. Any advice? >> [I trimmed a bit the list of recipients, sending to the mailing list is usually enough.] Ok, I gotta it and will keep attention in future.=20 Thanks! _______________________________________________ Best Regards Daniel Tian Mavrix Technology, Inc. Address=A3=BA200 Zhangheng Road, #3501, Building 3, Zhangjiang Hi-tech Park, Shanghai, P.R.China (201204)=20 Tel:86(21)51095958 - 8125 Fax:86(21)50277658 Email=A3=BAdaniel.tian@mavrixtech.com.cn www.mavrixtech.com