From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16723 invoked by alias); 27 Oct 2011 09:06:58 -0000 Received: (qmail 16701 invoked by uid 22791); 27 Oct 2011 09:06:57 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from shards.monkeyblade.net (HELO shards.monkeyblade.net) (198.137.202.13) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 27 Oct 2011 09:06:43 +0000 Received: from localhost (cpe-66-65-61-233.nyc.res.rr.com [66.65.61.233]) (authenticated bits=0) by shards.monkeyblade.net (8.14.4/8.14.4) with ESMTP id p9R96dOA013841 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 27 Oct 2011 02:06:42 -0700 Date: Thu, 27 Oct 2011 12:06:00 -0000 Message-Id: <20111027.050639.1769182268227861053.davem@davemloft.net> To: gcc@gcc.gnu.org Subject: cprop_reg problem on sparc From: David Miller Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2011-10/txt/msg00481.txt.bz2 Although copy_value() in regcprop.c tries to avoid recording cases where substitutions would be illegal, there are some bad cases it still can let through. On 64-bit sparc, integer regs are 64-bit and float regs are (basically) 32-bit. So HARD_REGNO_NREGS(float_reg, DFmode) is 2, and HARD_REGNO_NREGS(integer_reg, DImode) is 1. cprop sees the sequence: (insn 330 172 230 .. (set (reg:DI %g2) const_int) (insn 171 330 173 .. (set (reg:DF %f10) (reg:DF %g2))) (insn 173 171 222 .. (set (reg:DF %f2) (reg:DF %f10))) (insn 222 173 223 .. (set (MEM:SI ..) (reg:SI %f10))) (insn 223 222 174 .. (set (MEM:SI ..) (reg:SI %f11))) And then it believes that in insn 222 it can replace %f10 with %g2, but this is not a correct transformation. cprop uses hard_regno_nregs[][] to attempt to detect illegal cases like this one, but such checks will not trigger here because hard_regno_nregs[][] is '1' for all of the registers being inspected: hard_regno_nregs[][] (reg:SI f10) 1 hard_regno_nregs[][] (reg:DI g2) 1 The (set (reg:DI %g2) const_int) is generated by the *movdf_insn_sp64 insn which in turn triggers a splitter for loading float constants into integer registers. The MEM:SI stores are reloads generated by IRA for a pseudo that has to live across a call. For whatever reason it allocated only a 4-byte aligned stack location, and I suppose that is why the reload is split into 2 SImode pieces. To reproduce build gcc.c-torture/execute/ieee/mzero.c with "-m64 -mcpu=niagara3 -O2" on sparc. I'm suspecting that perhaps cprop is ok, and the real issue is that sparc's definition of CANNOT_CHANGE_MODE_CLASS needs to be adjusted.