From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25274 invoked by alias); 27 Oct 2011 13:18:38 -0000 Received: (qmail 25261 invoked by uid 22791); 27 Oct 2011 13:18:37 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from mel.act-europe.fr (HELO mel.act-europe.fr) (194.98.77.210) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 27 Oct 2011 13:18:21 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id B3F92CB01F9; Thu, 27 Oct 2011 15:18:21 +0200 (CEST) Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4A-2YcHpGjCA; Thu, 27 Oct 2011 15:18:12 +0200 (CEST) Received: from [192.168.1.2] (bon31-9-83-155-120-49.fbx.proxad.net [83.155.120.49]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id E6AEDCB0214; Thu, 27 Oct 2011 15:18:11 +0200 (CEST) From: Eric Botcazou To: David Miller Subject: Re: cprop_reg problem on sparc Date: Thu, 27 Oct 2011 18:21:00 -0000 User-Agent: KMail/1.9.9 Cc: gcc@gcc.gnu.org References: <20111027.050639.1769182268227861053.davem@davemloft.net> In-Reply-To: <20111027.050639.1769182268227861053.davem@davemloft.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <201110271517.40811.ebotcazou@adacore.com> Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2011-10/txt/msg00487.txt.bz2 > On 64-bit sparc, integer regs are 64-bit and float regs are > (basically) 32-bit. So HARD_REGNO_NREGS(float_reg, DFmode) is 2, and > HARD_REGNO_NREGS(integer_reg, DImode) is 1. > > cprop sees the sequence: > > (insn 330 172 230 .. (set (reg:DI %g2) const_int) > (insn 171 330 173 .. (set (reg:DF %f10) (reg:DF %g2))) > (insn 173 171 222 .. (set (reg:DF %f2) (reg:DF %f10))) > (insn 222 173 223 .. (set (MEM:SI ..) (reg:SI %f10))) > (insn 223 222 174 .. (set (MEM:SI ..) (reg:SI %f11))) > > And then it believes that in insn 222 it can replace %f10 with %g2, > but this is not a correct transformation. > > cprop uses hard_regno_nregs[][] to attempt to detect illegal cases > like this one, but such checks will not trigger here because > hard_regno_nregs[][] is '1' for all of the registers being inspected: > > hard_regno_nregs[][] (reg:SI f10) 1 > hard_regno_nregs[][] (reg:DI g2) 1 There seems to be a hole in the checks, as the number of registers is 2 for some of the intermediate steps. > To reproduce build gcc.c-torture/execute/ieee/mzero.c with > "-m64 -mcpu=niagara3 -O2" on sparc. AFAICS there is no such file as gcc.c-torture/execute/ieee/mzero.c. > I'm suspecting that perhaps cprop is ok, and the real issue is that > sparc's definition of CANNOT_CHANGE_MODE_CLASS needs to be adjusted. I'm a little skeptical at this point. -- Eric Botcazou