From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 131027 invoked by alias); 20 Feb 2019 19:24:58 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 123264 invoked by uid 89); 20 Feb 2019 19:24:52 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 spammy=choosing, H*Ad:U*amodra, H*i:sk:61bb9a5, H*f:sk:61bb9a5 X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 20 Feb 2019 19:24:51 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id x1KJOPS1006144; Wed, 20 Feb 2019 13:24:25 -0600 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id x1KJOKcb006142; Wed, 20 Feb 2019 13:24:20 -0600 Date: Wed, 20 Feb 2019 19:24:00 -0000 From: Segher Boessenkool To: Peter Bergner Cc: Alan Modra , GCC Subject: Re: Question regarding constraint usage within inline asm Message-ID: <20190220192418.GY14180@gate.crashing.org> References: <20190220030958.GC16787@bubble.grove.modra.org> <61bb9a58-0d4c-70e9-7611-3169de0c8950@linux.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <61bb9a58-0d4c-70e9-7611-3169de0c8950@linux.ibm.com> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2019-02/txt/msg00110.txt.bz2 On Wed, Feb 20, 2019 at 10:08:07AM -0600, Peter Bergner wrote: > On 2/19/19 9:09 PM, Alan Modra wrote: > > On Mon, Feb 18, 2019 at 01:13:31PM -0600, Peter Bergner wrote: > >> long input; > >> long > >> bug (void) > >> { > >> register long output asm ("r3"); > >> asm ("blah %0, %1, %2" : "=&r" (output) : "r" (input), "0" (input)); > >> return output; > >> } > > Without the asm("r3") gcc will provide your "blah" instruction with > > one register for %0 and %2, and another register for %1. Both > > registers will be initialised with the value of "input". > > That's not what I'm seeing. I see one pseudo (123) used for the output > operand and one pseudo (121) used for both input operands. Like so: > > (insn 8 6 7 (parallel [ > (set (reg:DI 123 [ outputD.2831 ]) > (asm_operands:DI ("blah %0, %1, %2") ("=&r") 0 [ > (reg/v:DI 121 [ ]) repeated x2 > ] > [ > (asm_input:DI ("r") bug.i:6) > (asm_input:DI ("0") bug.i:6) > ] > [] bug.i:6)) > (clobber (reg:SI 76 ca)) > ]) "bug.i":6:3 -1 > (nil)) expand already uses only one pseudo: ;; __asm__("blah %0, %1, %2" : "=&r" output : "r" input.0_1, "0" input.0_1); (insn 7 6 0 (parallel [ (set (reg/v:DI 3 3 [ output ]) (asm_operands:DI ("blah %0, %1, %2") ("=&r") 0 [ (reg:DI 121 [ input.0_1 ]) repeated x2 ] [ (asm_input:DI ("r") test.c:6) (asm_input:DI ("0") test.c:6) ] [] test.c:6)) (clobber (reg:SI 76 ca)) ]) "test.c":6:3 -1 (nil)) and that is a bad idea. The asmcons pass makes pseudo 121 equal to hard reg 3, and there is no way to recover from that. Without the local register asm you get the same pseudo for the output as well as both inputs, just as bad, but LRA can handle this: 0 Early clobber: reject++ 0 Conflict early clobber reload: reject-- alt=0,overall=6,losers=1,rld_nregs=0 Choosing alt 0 in insn 8: (0) =&r (1) r (2) 0 Creating newreg=126 from oldreg=123, assigning class GENERAL_REGS to r126 8: {r123:DI=asm_operands;clobber ca:SI;} REG_UNUSED ca:SI Inserting insn reload before: 19: r126:DI=r123:DI So expand shouldn't do this, but also asmcons should probably be improved Segher