Re: Expansion of narrowing math built-ins into power instructions

[Segher Boessenkool <segher@kernel.crashing.org>]

Hi!

On Mon, Jul 29, 2019 at 07:37:53PM +0200, Martin Jambor wrote:
> as you might know, Tejas is our Google Summer of Code student working on
> adding built-in functions for some new math functions added in ISO/IEC
> TS 18661.
> 
> His next step is to expand "functions rounding result to narrower type"
> (so fadd, fsub and possibly fmul and fdiv described in
> http://www.open-std.org/jtc1/sc22/wg14/www/docs/n2314.pdf) into ISA
> instructions on targets that have such instructions.  And Joseph
> suggested when he proposed this project that POWER8 (and I suppose also
> 9) is one of them.
> 
> Can you please confirm this and also perhaps point Tejas to the right
> pieces of power machine description and target code to emulate to
> implement expansion of these functions?  It would be very appreciated,
> because even though me and Honza are official mentors of the project, we
> are not very well versed in ppc target.

I think this is refering to the "fadds" and similar Power architecture
instructions, which take as inputs any single or double precision
numbers, and round the result to single precision?  These instructions
produce a correct result also for double-precision inputs, from ISA 2.07
(POWER8 and later) on.  (The result if OE=1 or UE=1 is undefined).  (See
4.3.5.1 in the ISA).

In GCC (in rs6000.md) we have the "*add<mode>3_fpr" and similar insns,
which could be extended to allow DF inputs with an SF output; it doesn't
yet allow it.

gcc112 is a Power8, and gcc135 is a Power9, and Tejas does have a
compile farm account already ;-)


Segher