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Date: Sat, 10 Aug 2019 16:12:00 -0000
From: Segher Boessenkool <segher@kernel.crashing.org>
To: John Darrington <john@darrington.wattle.id.au>
Cc: Vladimir Makarov <vmakarov@redhat.com>, Jeff Law <law@redhat.com>,        Paul Koning <paulkoning@comcast.net>, gcc@gcc.gnu.org
Subject: Re: Indirect memory addresses vs. lra
Message-ID: <20190810161218.GQ31406@gate.crashing.org>
References: <20190804191822.x4hwnfcyplnto3xc@jocasta.intra> <df260cfa-b749-063d-274b-f48d37450d47@redhat.com> <2B3A4EAB-D69E-4714-8FC4-C25E36B07BFF@comcast.net> <20190808172102.GH31406@gate.crashing.org> <2EEBCFAE-FF25-4664-AA5F-B3299CEA3CB1@comcast.net> <20190808191914.GK31406@gate.crashing.org> <dca38a3f-91db-9483-dd0e-0075ef501624@redhat.com> <20190809081439.baoyu3ii5i2qfbzt@jocasta.intra> <70b9bcc9-e12a-78b4-b8cc-a67b7ca3d38d@redhat.com> <20190810060553.m6e42sovw7s4xqoa@jocasta.intra>
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Hi!

On Sat, Aug 10, 2019 at 08:05:53AM +0200, John Darrington wrote:
> 	 Choosing alt 5 in insn 14:  (0) m  (1) m {*movsi}
>    14: [r40:PSI+0x20]=[r41:PSI]
>     Inserting insn reload before:
>    48: r40:PSI=r34:PSI
>    49: r41:PSI=[y:PSI+0x2f]

insn 14 is a mem-to-mem move (another feature not many more modern /
more RISCy CPUs have).  That requires both of your address registers.
So far, so good.  The reloads (insn 48 and 49) require address
registers themselves; that isn't necessarily a problem either.  But
this requires careful juggling.  Maybe you will need some backend code
for this, or to optimise this (although right now you just want it to
*work* :-) )

For some reason LRA didn't manage.  Register inheritance seems to be
implicated (but that might be a red herring).  Vladimir will probably
find out more, and/or correct me :-)


Segher