From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 69950 invoked by alias); 20 Aug 2019 07:07:36 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 69936 invoked by uid 89); 20 Aug 2019 07:07:35 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-5.1 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.1 spammy=H*i:sk:fmf6tn2, H*f:sk:fmf6tn2, H*i:CAFiYyc2ER5kvra, H*f:CAFiYyc2ER5kvra X-HELO: jocasta.intra Received: from de.cellform.com (HELO jocasta.intra) (88.217.224.109) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Aug 2019 07:07:33 +0000 Received: from jocasta.intra (localhost [127.0.0.1]) by jocasta.intra (8.15.2/8.15.2/Debian-8) with ESMTPS id x7K77UjS019550 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Aug 2019 09:07:30 +0200 Received: (from john@localhost) by jocasta.intra (8.15.2/8.15.2/Submit) id x7K77U4A019549; Tue, 20 Aug 2019 09:07:30 +0200 Date: Tue, 20 Aug 2019 07:07:00 -0000 From: John Darrington To: Richard Biener Cc: John Darrington , Segher Boessenkool , Vladimir Makarov , GCC Development Subject: Re: Special Memory Constraint [was Re: Indirect memory addresses vs. lra] Message-ID: <20190820070729.efox77kw3jhovswh@jocasta.intra> References: <20190815173559.kbp3uja7jklx74iy@jocasta.intra> <3c6c87ce-a38f-728d-e083-aa066d531790@redhat.com> <20190816112357.ep7fns6skm5emoey@jocasta.intra> <5693be1f-4351-94ab-9096-f6e4f9f875c1@redhat.com> <20190819073553.pi644qzyokxmynr2@jocasta.intra> <16f173b7-d835-48f9-aaed-d5d38d4748ca@redhat.com> <20190819150711.GL31406@gate.crashing.org> <20190819180644.wn7s2dxdgjlwvdw7@jocasta.intra> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) X-IsSubscribed: yes X-SW-Source: 2019-08/txt/msg00151.txt.bz2 On Tue, Aug 20, 2019 at 08:56:39AM +0200, Richard Biener wrote: > Most of these suggestions involve adding some sort of virtual registers > So I hacked the machine description to add two new registers Z1 and Z2 > with the same mode as X and Y. > > Obviously the assembler balks at this. However the compiler still > ICEs at the same place as before. > > So this suggests that our original diagnosis, viz: there are not enough > address registers was not accurate, and in fact there is some other > problem? That sounds likely. Given you have indirect addressing you could simulate N virtual regs by placing them in a virtual reg table in memory and accessed via a fixed address register (assuming all instructions that would need an address reg also can take that indirect from memory). That was my plan. Accordingly, extending the md to provide N additional regs (N currently = 2) was the first step. Having doubled the number of available address registers, I had expected this would fix most of the ICEs (but cause a lot of assembler errors). However it hasn't eliminated any ICEs. lra is still complaining "unable to find a register to spill" So the plan seems to have fallen over at the first hurdle. Why can it still not spill registers despite having a lot more of them? J'