From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jeffrey A Law <law@cygnus.com>
To: Bill Currie <bcurrie@tssc.co.nz>
Cc: Joern Rennecke <amylaar@cygnus.co.uk>, ak@muc.de, egcs@cygnus.com
Subject: Re: Feature request: ability to describe x86 register halves as contraints. 
Date: Thu, 02 Jul 1998 01:39:00 -0000
Message-id: <23540.899348404@hurl.cygnus.com>
References: <359ABD84.2FC4@tssc.co.nz>
X-SW-Source: 1998-07/msg00077.html

  In message <359ABD84.2FC4@tssc.co.nz>you write:
  > Jeffrey A Law wrote:
  > > I guess that would be OK.  I'm still not convinced it's worth the huge
  > > effort though.
  > > jeff
  > 
  > Sometimes I think the amount of effort required is grossly
  > over-estimated (but not allways).
I disagree.  One of the things I do for Cygnus is estimations and
estimation review -- my opinions based on that would tend to be just
the opposite.  While many problems seem easy on the surface, when you
dig deeper you often find fundamental problems that throw off estimations
by  2X-5X.


  > I recently disproved the comment in
  > config/i860/i860.h about the difficulty of gcc supporting cross endian
  > cpu's (ie reg word endian != mem word endian) buy totaly confusing gcc
  > as to what subreg 1 was (I told final.c that subreg 1 was (eg) %r8
  > instead of %r9 :).
And whie this may be working for you, I highly suspect if you dig deeper
you'll find out that all kinds of things eventually break.


  > I haven't submitted any patches yet, because I
  > totally broke the *little* endian i860 (i860.md only) and I'm still
  > finding numberous md bugs that where there at the start (incorrect
  > constraints etc), and I still have to forward port my patches to the
  > latest CVS sources.
The i860 port is probably buggy as hell.  Nobody's working on it at all.


  > One question, would the following work, or would it break insn
  > recognition?
  > 
  > (define_expand "fix_truncdfsi2"
  >   ;; This first insn produces a double-word value
  >   ;; in which only the low word is valid.
  >   [(set (match_dup 2)
  > 	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
  >    (set (match_operand:SI 0 "register_operand" "=f")
  > 	(match_dup 3))] /*this used to be (subreg (SI (match_dup 2) 1)*/
  >   ""
  >   "
  > {
  >   operands[2] = gen_reg_rtx (DImode);
  >   operands[3] = gen_rtx_SUBREG (SImode, operands[2], WORDS_BIG_ENDIAN);
  > }")
  > 
  > I would like to do this so i860 endian selection can be a target switch.
I would think this will work as long as you have appropriate matchers.

However, I'm curious how you deal with memory subregs or register
subregs that get spilled, then loaded from memory.  I get the
impression that how the word of a subreg is interpreted changes based
on what the inner object is.

jeff