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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id o5-20020a170902d4c500b001886863c6absm277429plg.97.2022.11.04.16.13.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Nov 2022 16:13:21 -0700 (PDT) Message-ID: <2541e77f-f069-13d1-c08e-47f55677a596@gmail.com> Date: Fri, 4 Nov 2022 17:13:20 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: query about commit 666fdc46bc8489 ("RISC-V: Fix bad insn splits with paradoxical subregs") Content-Language: en-US To: Vineet Gupta , Jakub Jelinek Cc: gcc@gcc.gnu.org, Michael Collison References: <23ac9d02-c687-7680-493b-8ace1558a4cb@rivosinc.com> From: Jeff Law In-Reply-To: <23ac9d02-c687-7680-493b-8ace1558a4cb@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/4/22 16:59, Vineet Gupta wrote: > Hi Jakub, > > I had a question about the aforementioned commit in RV backend. > > (define_split >   [(set (match_operand:GPR 0 "register_operand") >     (and:GPR (match_operand:GPR 1 "register_operand") >                (match_operand:GPR 2 "p2m1_shift_operand"))) > +   (clobber (match_operand:GPR 3 "register_operand"))] >   "" > -  [(set (match_dup 0) > +  [(set (match_dup 3) >        (ashift:GPR (match_dup 1) (match_dup 2))) > > Is there something specific to this split which warrants this or so > any split patterns involving shifts have this to avoid the shifting by > more than SUBREG_REG problem. Not sure.  Note it was Jim Wilson's change, not Jakub's change AFAICT: commit 666fdc46bc848984ee7d2906f2dfe10e1ee5d535 Author: Jim Wilson Date:   Sat Jun 30 21:52:01 2018 +0000     RISC-V: Add patterns to convert AND mask to two shifts.             gcc/             * config/riscv/predicates.md (p2m1_shift_operand): New.             (high_mask_shift_operand): New.             * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): New combiner             pattern using p2m1_shift_operand.             (lshsi3_zero_extend_3+2): New combiner pattern using             high_mask_shift_operand.             gcc/testsuite/             * gcc.target/riscv/shift-shift-1.c: New.             * gcc.target/riscv/shift-shift-2.c: New.             * gcc.target/riscv/shift-shift-3.c: New.     From-SVN: r262278 You might find further discussion in the gcc-patches archives. > > Also could you please explain where the clobber itself is allocated ? I'd expect the combiner.   There's going to be 2 or more insns that are combined to create this pattern where the output of one feeds a subsequent insn and dies.  So it's effectively a temporary.  Combine will re-use that temporary as the clobbered operand. Jeff