* New target for Coldfire v4e?
@ 2004-12-13 7:20 C Jaiprakash, Noida
2004-12-13 13:27 ` Bernardo Innocenti
0 siblings, 1 reply; 19+ messages in thread
From: C Jaiprakash, Noida @ 2004-12-13 7:20 UTC (permalink / raw)
To: gcc; +Cc: peter, schwab
Hi,
I want to submit the changes for ColdFire v4e. But to get m68k-linux
target working for ColdFire v4e i had to make some changes in the m68k-linux
target configuration. I had to modify t-linux for multi-lib part. Will these
changes be acceptable or do i have to create a new target for ex.
coldfire-linux?
Thanks and best regards,
C Jaiprakash
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Contributing to the World by creating indispensable value !
System Software CoE @ HCLT-Noida
http://www.hcltechnologies.com
Ph. : +91-120-2510701/702 Ext : 3170
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> -----Original Message-----
> From: gcc-owner@gcc.gnu.org [mailto:gcc-owner@gcc.gnu.org]On
> Behalf Of C
> Jaiprakash, Noida
> Sent: Wednesday, November 17, 2004 12:01 PM
> To: gcc@gcc.gnu.org
> Cc: peter@the-baradas.com; schwab@suse.de
> Subject: ColdFire V4e port submission
>
>
> Hi,
> I recently completed ColdFire v4e port based on Peter Barada's
> implementation in gcc 3.4, binutils 2.15.9x and glibc 2.3.2.
> It includes
> FPU support for coldfire v4e and pic support. Using this
> toolchain I could
> succefully build and boot 2.4 linux kernel and all other applications
> (coreutils, busybox etc) with static and dynamic linking on
> coldfire 5485
> board. Is it possible that these changes can be commited into
> gcc 3.4?
>
> Thanks Peter and Andreas for your help.
>
> Thanks and best regards,
> C Jaiprakash
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Contributing to the World by creating indispensable value !
>
> System Software CoE @ HCLT-Noida
> http://www.hcltechnologies.com
> Ph. : +91-120-2510701/702 Ext : 3170
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-13 7:20 New target for Coldfire v4e? C Jaiprakash, Noida
@ 2004-12-13 13:27 ` Bernardo Innocenti
2004-12-13 14:30 ` Peter Barada
0 siblings, 1 reply; 19+ messages in thread
From: Bernardo Innocenti @ 2004-12-13 13:27 UTC (permalink / raw)
To: C Jaiprakash, Noida; +Cc: gcc, peter, schwab
C Jaiprakash, Noida wrote:
> Hi,
> I want to submit the changes for ColdFire v4e.
That's very good news indeed!
GCC's main development branch is currently in stage 3; that
means only regression fixes are being accepted at the moment.
To save time, you may start submitting patches now, but
we'll have to wait until the development of GCC 4.1 resumes
in order to commit them.
Are you already familiar with rules for contributing to GCC?
If not, read http://gcc.gnu.org/contribute.html and make
sure your patches conform to these rules.
To help reviewers, please break your changes in small pieces,
motivating each patch. To get some early feedback, feel free
to post your patches even before they're completely polished,
but say so in the description.
After the first round of reviews, some of your work may need
fixes, improvements or documentation changes. This process
may require a few weeks of calendar time (and a few hours of
your time).
Be sure to go through the legal papers, otherwise we won't
be able to accept your changes in our codebase.
> But to get m68k-linux
> target working for ColdFire v4e i had to make some changes in
> the m68k-linux target configuration.
Do you also support the m68k-uclinux target? That would be
highly desiderable, since many ColdFire platform use the
uClinux kernel and distribution.
Also, the m68k-elf (for bare-metal embedded systems) and
m68k-rtems targets may want to use the new processor.
If you didn't update these targets, that can also be taken
care of later with followup patches from you or other
contributors.
> I had to modify t-linux for multi-lib part. Will these
> changes be acceptable or do i have to create a new target for ex.
> coldfire-linux?
That depends on how your changes affect other m68k-linux
users. If you removed 680x0 processors, you certaily need
to create a different target triplet.
I'm sure we *can* keep v4e along with other m68k targets.
Most of your changes are probably processor-specific (new
instructions, etc.). These can easily be shared.
The other changes to the m68k-linux target are probably
meant to generate multilibbed libraries for the new m68k
variant, these can be shared too.
Does m68k-linux have some special requirements such
as tweaks to the ELF format for shared-library support?
The uClinux target has *many* such tricks and thus it's
been made a separate target.
--
// Bernardo Innocenti - Develer S.r.l., R&D dept.
\X/ http://www.develer.com/
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-13 13:27 ` Bernardo Innocenti
@ 2004-12-13 14:30 ` Peter Barada
2004-12-13 18:13 ` Bernardo Innocenti
0 siblings, 1 reply; 19+ messages in thread
From: Peter Barada @ 2004-12-13 14:30 UTC (permalink / raw)
To: bernie; +Cc: cjaiprakash, gcc, schwab
>> I want to submit the changes for ColdFire v4e.
>
>That's very good news indeed!
>
>GCC's main development branch is currently in stage 3; that
>means only regression fixes are being accepted at the moment.
>
>To save time, you may start submitting patches now, but
>we'll have to wait until the development of GCC 4.1 resumes
>in order to commit them.
Before you submit any patches, a very strong suggestion is to check
out a current version of gcc(or snag a current snapshot), put it into
a local CVS repository and make your changes to that to support
ColdFire v4e, that way you know:
1) That the changes you want to make work against the current compiler
2) Exactly what parts need to change.
This approach will naturally lead you to breaking up the diffs to your
CVS repository into bite-sized pieces, especially if you break up the
checkins to your CVS tree.
>> I had to modify t-linux for multi-lib part. Will these
>> changes be acceptable or do i have to create a new target for ex.
>> coldfire-linux?
>
>That depends on how your changes affect other m68k-linux
>users. If you removed 680x0 processors, you certaily need
>to create a different target triplet.
>
>I'm sure we *can* keep v4e along with other m68k targets.
>Most of your changes are probably processor-specific (new
>instructions, etc.). These can easily be shared.
>
>The other changes to the m68k-linux target are probably
>meant to generate multilibbed libraries for the new m68k
>variant, these can be shared too.
>
>Does m68k-linux have some special requirements such
>as tweaks to the ELF format for shared-library support?
Since PIC support for m68k uses a mode-6 variant to acheive 32-bit
register offset addressing, and ColdFire doesn't support that
addressing mode, then changes needed to be made for PIC addressing
support.
>The uClinux target has *many* such tricks and thus it's
>been made a separate target.
I'd suggest a new target (--target=coldfire-linux) just to seperate
the changes and make it much easier to make sure that you don't break
m68k-linux. This will dovetail with the add-on in glibc to support
ColdFire as well...
--
Peter Barada
peter@the-baradas.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-13 14:30 ` Peter Barada
@ 2004-12-13 18:13 ` Bernardo Innocenti
2004-12-13 18:43 ` Peter Barada
0 siblings, 1 reply; 19+ messages in thread
From: Bernardo Innocenti @ 2004-12-13 18:13 UTC (permalink / raw)
To: Peter Barada; +Cc: cjaiprakash, gcc, schwab
Peter Barada wrote:
>>> I want to submit the changes for ColdFire v4e.
>>
>>That's very good news indeed!
>>
>>GCC's main development branch is currently in stage 3; that
>>means only regression fixes are being accepted at the moment.
>>
>>To save time, you may start submitting patches now, but
>>we'll have to wait until the development of GCC 4.1 resumes
>>in order to commit them.
>
>
> Before you submit any patches, a very strong suggestion is to check
> out a current version of gcc(or snag a current snapshot), put it into
> a local CVS repository and make your changes to that to support
> ColdFire v4e, that way you know:
>
> 1) That the changes you want to make work against the current compiler
> 2) Exactly what parts need to change.
>
> This approach will naturally lead you to breaking up the diffs to your
> CVS repository into bite-sized pieces, especially if you break up the
> checkins to your CVS tree.
I second Peter's suggestion, except that I find it more comfortable
to skip the local CVS part and go the "linux kernel way".
I tend to apply my patches to a local snapshot (or CVS checkout) of
GCC, keeping the vanilla copy around for diffing.
When you have many patches over the same files, sometimes two patches
have overlapping parts and need to be applied in a particular order.
When I want to change something, I first revert overlapping patches.
This modus-operandi requires much care, but it gives you greater
flexibility than CVS does and helps you keep the changes .
When you submit several patches, they may be reviewed and approved
out-of-order. Some patches will have to be reworked and resubmitted,
along with an updated ChangeLog.
So I prefer to keep patches in this higher-level format (diff +
ChangeLog + patch discussion) which also lets you make simple
fixes by hacking the diff hunks.
Sometimes you're lucky and most patches apply cleanly to several
GCC versions at once, so you don't have to synchronize your
changes with several branches or repositories.
>>Does m68k-linux have some special requirements such
>>as tweaks to the ELF format for shared-library support?
>
> Since PIC support for m68k uses a mode-6 variant to acheive 32-bit
> register offset addressing, and ColdFire doesn't support that
> addressing mode, then changes needed to be made for PIC addressing
> support.
This would be an m68k.md/m68k.c change only, wouldn't it?
Not something that would affect the binary format...
uClinux required that FLAT file format and -mid-shared-library
mess to support shared libraries with UNIX semantics without
an MMU.
>>The uClinux target has *many* such tricks and thus it's
>>been made a separate target.
>
> I'd suggest a new target (--target=coldfire-linux) just to seperate
> the changes and make it much easier to make sure that you don't break
> m68k-linux.
Without seeing what changes he made, I'm not really sure what
would be the best option...
Besides, adding a new target *can* be approved in stage 3, unless
of course the new code affects other targets. My guess is that
adding v4e support impacts m68k.md and m68k.c *much* more than
the t-linux parts we're discussing, so it won't qualify for 4.0.
C Jaiprakash, could you please send us your patches for
a first look? No need to polish them up...
> This will dovetail with the add-on in glibc to support
> ColdFire as well...
Couldn't glibc just use __mcoldfire__ to take care of ColdFire
peculiarities? I'd expect most of the m68k parts to be usable
on ColdFire.
--
// Bernardo Innocenti - Develer S.r.l., R&D dept.
\X/ http://www.develer.com/
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-13 18:13 ` Bernardo Innocenti
@ 2004-12-13 18:43 ` Peter Barada
2004-12-14 1:08 ` Bernardo Innocenti
0 siblings, 1 reply; 19+ messages in thread
From: Peter Barada @ 2004-12-13 18:43 UTC (permalink / raw)
To: bernie; +Cc: cjaiprakash, gcc, schwab
>> This approach will naturally lead you to breaking up the diffs to your
>> CVS repository into bite-sized pieces, especially if you break up the
>> checkins to your CVS tree.
>
>I second Peter's suggestion, except that I find it more comfortable
>to skip the local CVS part and go the "linux kernel way".
>
>I tend to apply my patches to a local snapshot (or CVS checkout) of
>GCC, keeping the vanilla copy around for diffing.
I don't want to argue the merits of a local CVS repository vs a local
copy, but 'cvs diff -r1.1' will diff against the vanilla version, and
'cvs -q diff -c3p' produces ready to submit patches :)
>>>Does m68k-linux have some special requirements such
>>>as tweaks to the ELF format for shared-library support?
>>
>> Since PIC support for m68k uses a mode-6 variant to acheive 32-bit
>> register offset addressing, and ColdFire doesn't support that
>> addressing mode, then changes needed to be made for PIC addressing
>> support.
>
>This would be an m68k.md/m68k.c change only, wouldn't it?
>Not something that would affect the binary format...
>
>uClinux required that FLAT file format and -mid-shared-library
>mess to support shared libraries with UNIX semantics without
>an MMU.
Then the answer to your first question is no. The changes are to
m68k.h/m68k.c,m68k.md, as well as the t-linux file and I'd have to go
back and look, but I think maybe one or two others(pretty small
stuff), all in gcc/config/m68k.
gerg@snapgear.com already has a 547x/548x uClinux version(its in the
uclinux CVS tree), using the FLAT file format. I'm assuming it uses
the current m68k-uclinux target.
>> I'd suggest a new target (--target=coldfire-linux) just to seperate
>> the changes and make it much easier to make sure that you don't break
>> m68k-linux.
>
>Without seeing what changes he made, I'm not really sure what
>would be the best option...
The more I work in this area, the more I think ColdFire should split
off into its own config directory.
>Besides, adding a new target *can* be approved in stage 3, unless
>of course the new code affects other targets. My guess is that
>adding v4e support impacts m68k.md and m68k.c *much* more than
>the t-linux parts we're discussing, so it won't qualify for 4.0.
I'm sure it won't make it into 4.0.
I see from the development plan that 4.0 is not going to split off
until early '05, so getting bite-sized patches that reviewers can
understand and approve(but not commit) will make it easier for other
people who want to develop in this area.
--
Peter Barada
peter@the-baradas.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-13 18:43 ` Peter Barada
@ 2004-12-14 1:08 ` Bernardo Innocenti
2004-12-14 2:24 ` Peter Barada
2004-12-14 2:34 ` Peter Barada
0 siblings, 2 replies; 19+ messages in thread
From: Bernardo Innocenti @ 2004-12-14 1:08 UTC (permalink / raw)
To: Peter Barada; +Cc: cjaiprakash, gcc, schwab
Peter Barada wrote:
>>I tend to apply my patches to a local snapshot (or CVS checkout) of
>>GCC, keeping the vanilla copy around for diffing.
>
> I don't want to argue the merits of a local CVS repository vs a local
> copy, but 'cvs diff -r1.1' will diff against the vanilla version, and
> 'cvs -q diff -c3p' produces ready to submit patches :)
You mean a single huge patch? How do you split the pieces
apart?
>>uClinux required that FLAT file format and -mid-shared-library
>>mess to support shared libraries with UNIX semantics without
>>an MMU.
>
> Then the answer to your first question is no. The changes are to
> m68k.h/m68k.c,m68k.md, as well as the t-linux file and I'd have to go
> back and look, but I think maybe one or two others(pretty small
> stuff), all in gcc/config/m68k.
Are these changes disruptive for other m68k targets?
> gerg@snapgear.com already has a 547x/548x uClinux version(its in the
> uclinux CVS tree), using the FLAT file format. I'm assuming it uses
> the current m68k-uclinux target.
Last time I checked uClinux's CVS repository and web site, there
were no clues about upcoming v4e support.
It seems this whole development is happening behind a curtain.
NDAs or what?
>>Without seeing what changes he made, I'm not really sure what
>>would be the best option...
>
> The more I work in this area, the more I think ColdFire should split
> off into its own config directory.
I tend to agree, perhaps sharing some common code. Targets such
as RTEMS and uClinux may want to support both architectures while
retaining consistency in target macros such as TARGET_OS_CPP_BUILTINS.
>>Besides, adding a new target *can* be approved in stage 3, unless
>>of course the new code affects other targets. My guess is that
>>adding v4e support impacts m68k.md and m68k.c *much* more than
>>the t-linux parts we're discussing, so it won't qualify for 4.0.
>
> I'm sure it won't make it into 4.0.
Perhaps it'd better if it lives as an external patchset for a while,
like many new targets do in their infancy.
> I see from the development plan that 4.0 is not going to split off
> until early '05, so getting bite-sized patches that reviewers can
> understand and approve(but not commit) will make it easier for other
> people who want to develop in this area.
The long-term goal may be full-merge, but in the meanwhile you
could get to merge trivial preparatory patches to setup the ground.
Besides, have you already submitted patches for config.sub and
config.guess to the configury project? And what about as/ld changes?
--
// Bernardo Innocenti - Develer S.r.l., R&D dept.
\X/ http://www.develer.com/
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 1:08 ` Bernardo Innocenti
@ 2004-12-14 2:24 ` Peter Barada
2004-12-14 2:34 ` Peter Barada
1 sibling, 0 replies; 19+ messages in thread
From: Peter Barada @ 2004-12-14 2:24 UTC (permalink / raw)
To: bernie; +Cc: cjaiprakash, gcc, schwab
>>>I tend to apply my patches to a local snapshot (or CVS checkout) of
>>>GCC, keeping the vanilla copy around for diffing.
>>
>> I don't want to argue the merits of a local CVS repository vs a local
>> copy, but 'cvs diff -r1.1' will diff against the vanilla version, and
>> 'cvs -q diff -c3p' produces ready to submit patches :)
>
>You mean a single huge patch? How do you split the pieces
>apart?
Ah, no.
What I meant is that if you use a local CVS repository, you can
introduce each change, and tag the database as you integrate them. Then
you can produce patches using 'cvs diff' from tag-to-tag which keeps each
patch down to a bite-size piece.
--
Peter Barada
peter@the-baradas.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 1:08 ` Bernardo Innocenti
2004-12-14 2:24 ` Peter Barada
@ 2004-12-14 2:34 ` Peter Barada
2004-12-14 8:26 ` Bernardo Innocenti
1 sibling, 1 reply; 19+ messages in thread
From: Peter Barada @ 2004-12-14 2:34 UTC (permalink / raw)
To: bernie; +Cc: cjaiprakash, gcc, schwab
>>>uClinux required that FLAT file format and -mid-shared-library
>>>mess to support shared libraries with UNIX semantics without
>>>an MMU.
>>
>> Then the answer to your first question is no. The changes are to
>> m68k.h/m68k.c,m68k.md, as well as the t-linux file and I'd have to go
>> back and look, but I think maybe one or two others(pretty small
>> stuff), all in gcc/config/m68k.
>
>Are these changes disruptive for other m68k targets?
Hopefully not, but they do affect commen code generation macros and
functions.
>> gerg@snapgear.com already has a 547x/548x uClinux version(its in the
>> uclinux CVS tree), using the FLAT file format. I'm assuming it uses
>> the current m68k-uclinux target.
>
>Last time I checked uClinux's CVS repository and web site, there
>were no clues about upcoming v4e support.
>
>It seems this whole development is happening behind a curtain.
>NDAs or what?
I beleive that I"ve checked out the uclinux tree with support for the
547x target in it, Greg and verify that. This work hasn't been done
under NDAs, just that it isn't worth exposing it until it is known to
work. I haven't signed any NDA to see the work thus far, and you've
seen that Freescale is trying to get it integrated back into the
mainline tree.
>>>Without seeing what changes he made, I'm not really sure what
>>>would be the best option...
>>
>> The more I work in this area, the more I think ColdFire should split
>> off into its own config directory.
>
>I tend to agree, perhaps sharing some common code. Targets such
>as RTEMS and uClinux may want to support both architectures while
>retaining consistency in target macros such as TARGET_OS_CPP_BUILTINS.
I'm looking at splitting off the gcc/config/m68k directory into
gcc/config/coldfire for some of this and future work and adding
configs or coldfire-elf and coldfire-linux...
>>>Besides, adding a new target *can* be approved in stage 3, unless
>>>of course the new code affects other targets. My guess is that
>>>adding v4e support impacts m68k.md and m68k.c *much* more than
>>>the t-linux parts we're discussing, so it won't qualify for 4.0.
>>
>> I'm sure it won't make it into 4.0.
>
>Perhaps it'd better if it lives as an external patchset for a while,
>like many new targets do in their infancy.
Your probably right, but the quicker that they are seen teh quicker
they can be revamped into something acceptable to the mainline.
>> I see from the development plan that 4.0 is not going to split off
>> until early '05, so getting bite-sized patches that reviewers can
>> understand and approve(but not commit) will make it easier for other
>> people who want to develop in this area.
>
>The long-term goal may be full-merge, but in the meanwhile you
>could get to merge trivial preparatory patches to setup the ground.
>
>Besides, have you already submitted patches for config.sub and
>config.guess to the configury project? And what about as/ld changes?
Any prepatory patched have to wait until mainline gets out of stage 3
unless the release manager doesn't care about changes to gcc that
affect a non primary or secondary port. as/ld already support
-mcfv4e.
I don't think any patches have been submitted for config.sub.
--
Peter Barada
peter@the-baradas.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 2:34 ` Peter Barada
@ 2004-12-14 8:26 ` Bernardo Innocenti
2004-12-14 14:24 ` Peter Barada
2004-12-17 14:10 ` Gunther Nikl
0 siblings, 2 replies; 19+ messages in thread
From: Bernardo Innocenti @ 2004-12-14 8:26 UTC (permalink / raw)
To: Peter Barada; +Cc: cjaiprakash, gcc, schwab
Peter Barada wrote:
>>It seems this whole development is happening behind a curtain.
>>NDAs or what?
>
> I beleive that I"ve checked out the uclinux tree with support for the
> 547x target in it, Greg and verify that. This work hasn't been done
> under NDAs, just that it isn't worth exposing it until it is known to
> work. I haven't signed any NDA to see the work thus far, and you've
> seen that Freescale is trying to get it integrated back into the
> mainline tree.
Fine. Are you also going to integrate patches into the Linux kernel?
I've read you've ported 2.4... what about 2.6?
It's too bad I don't have the hardware... not that I could help
much, but it would be fun to try :-)
>>I tend to agree, perhaps sharing some common code. Targets such
>>as RTEMS and uClinux may want to support both architectures while
>>retaining consistency in target macros such as TARGET_OS_CPP_BUILTINS.
>
> I'm looking at splitting off the gcc/config/m68k directory into
> gcc/config/coldfire for some of this and future work and adding
> configs or coldfire-elf and coldfire-linux...
You'd also need to move m68k-uclinux to coldfire-uclinux. Actually,
there was a port of uClinux to the 68000 (Amiga 500) and DragonBall
(Palm II), but these are mostly unofficial.
Are you also going to cleanup the m68k target by removing the
ColdFire bits?
>>Perhaps it'd better if it lives as an external patchset for a while,
>>like many new targets do in their infancy.
>
> Your probably right, but the quicker that they are seen teh quicker
> they can be revamped into something acceptable to the mainline.
I'm also a fan of "release early, release often" and
"many eyes make all bugs shallow" (Linus).
>>Besides, have you already submitted patches for config.sub and
>>config.guess to the configury project? And what about as/ld changes?
>
> Any prepatory patched have to wait until mainline gets out of stage 3
> unless the release manager doesn't care about changes to gcc that
> affect a non primary or secondary port. as/ld already support
> -mcfv4e.
Good.
> I don't think any patches have been submitted for config.sub.
Once they're accepted (the maintainer will usually ask to make
sure the target really exists and has some kind of userbase),
anyone can import the latest version in the ggo and src CVS
trees.
--
// Bernardo Innocenti - Develer S.r.l., R&D dept.
\X/ http://www.develer.com/
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 8:26 ` Bernardo Innocenti
@ 2004-12-14 14:24 ` Peter Barada
2004-12-14 18:34 ` Bernardo Innocenti
2004-12-17 14:10 ` Gunther Nikl
1 sibling, 1 reply; 19+ messages in thread
From: Peter Barada @ 2004-12-14 14:24 UTC (permalink / raw)
To: bernie; +Cc: cjaiprakash, gcc, schwab
>> I'm looking at splitting off the gcc/config/m68k directory into
>> gcc/config/coldfire for some of this and future work and adding
>> configs or coldfire-elf and coldfire-linux...
>
>You'd also need to move m68k-uclinux to coldfire-uclinux. Actually,
>there was a port of uClinux to the 68000 (Amiga 500) and DragonBall
>(Palm II), but these are mostly unofficial.
>
>Are you also going to cleanup the m68k target by removing the
>ColdFire bits?
If people would buy into the concept so its not all wasted work, then
yes, I'd pull all the ColdFire bits out of gcc/config/m68k and place
them in gcc/config/coldfire.
--
Peter Barada
peter@the-baradas.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 14:24 ` Peter Barada
@ 2004-12-14 18:34 ` Bernardo Innocenti
2004-12-14 20:14 ` Joel Sherrill <joel@OARcorp.com>
0 siblings, 1 reply; 19+ messages in thread
From: Bernardo Innocenti @ 2004-12-14 18:34 UTC (permalink / raw)
To: Peter Barada; +Cc: cjaiprakash, gcc, schwab
Peter Barada wrote:
>>>I'm looking at splitting off the gcc/config/m68k directory into
>>>gcc/config/coldfire for some of this and future work and adding
>>>configs or coldfire-elf and coldfire-linux...
>>
>>You'd also need to move m68k-uclinux to coldfire-uclinux. Actually,
>>there was a port of uClinux to the 68000 (Amiga 500) and DragonBall
>>(Palm II), but these are mostly unofficial.
>>
>>Are you also going to cleanup the m68k target by removing the
>>ColdFire bits?
>
>
> If people would buy into the concept so its not all wasted work, then
> yes, I'd pull all the ColdFire bits out of gcc/config/m68k and place
> them in gcc/config/coldfire.
We're talking about slimming m68k.md by about 500 lines here and
simplifying m68k.c in many places. That would be yummie.
However, I'm concerned about code duplication. Many bugs would
certainly still affect both backends and many improvements would
be applicable to both.
Couldn't we "split" the m68k backend in three parts instead?
A core part (m68k) containing all common code and two backends
based on it: m680x0 and coldfire. (CPU32 would stay with the
68000 of course).
This would require slightly more work initially, but it would
reduce maintenance costs in the long term.
--
// Bernardo Innocenti - Develer S.r.l., R&D dept.
\X/ http://www.develer.com/
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 18:34 ` Bernardo Innocenti
@ 2004-12-14 20:14 ` Joel Sherrill <joel@OARcorp.com>
2004-12-14 20:57 ` Peter Barada
0 siblings, 1 reply; 19+ messages in thread
From: Joel Sherrill <joel@OARcorp.com> @ 2004-12-14 20:14 UTC (permalink / raw)
To: Bernardo Innocenti; +Cc: Peter Barada, cjaiprakash, gcc, schwab
Bernardo Innocenti wrote:
> Peter Barada wrote:
>
>>>> I'm looking at splitting off the gcc/config/m68k directory into
>>>> gcc/config/coldfire for some of this and future work and adding
>>>> configs or coldfire-elf and coldfire-linux...
>>>
>>>
>>> You'd also need to move m68k-uclinux to coldfire-uclinux. Actually,
>>> there was a port of uClinux to the 68000 (Amiga 500) and DragonBall
>>> (Palm II), but these are mostly unofficial.
>>>
>>> Are you also going to cleanup the m68k target by removing the
>>> ColdFire bits?
>>
>>
>>
>> If people would buy into the concept so its not all wasted work, then
>> yes, I'd pull all the ColdFire bits out of gcc/config/m68k and place
>> them in gcc/config/coldfire.
>
>
> We're talking about slimming m68k.md by about 500 lines here and
> simplifying m68k.c in many places. That would be yummie.
>
> However, I'm concerned about code duplication. Many bugs would
> certainly still affect both backends and many improvements would
> be applicable to both.
>
> Couldn't we "split" the m68k backend in three parts instead?
> A core part (m68k) containing all common code and two backends
> based on it: m680x0 and coldfire. (CPU32 would stay with the
> 68000 of course).
>
> This would require slightly more work initially, but it would
> reduce maintenance costs in the long term.
>
I have been following this and want to make sure I am understanding.
Would there now be separate m68k and coldfire targets? Said another
way, would m68k-XYZ be able to include Coldfire support?
-
Joel Sherrill, Ph.D. Director of Research & Development
joel@OARcorp.com On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 20:14 ` Joel Sherrill <joel@OARcorp.com>
@ 2004-12-14 20:57 ` Peter Barada
2004-12-14 21:41 ` Joel Sherrill <joel@OARcorp.com>
0 siblings, 1 reply; 19+ messages in thread
From: Peter Barada @ 2004-12-14 20:57 UTC (permalink / raw)
To: joel.sherrill; +Cc: bernie, cjaiprakash, gcc, schwab
>>> If people would buy into the concept so its not all wasted work, then
>>> yes, I'd pull all the ColdFire bits out of gcc/config/m68k and place
>>> them in gcc/config/coldfire.
>>
>>
>> We're talking about slimming m68k.md by about 500 lines here and
>> simplifying m68k.c in many places. That would be yummie.
>>
>> However, I'm concerned about code duplication. Many bugs would
>> certainly still affect both backends and many improvements would
>> be applicable to both.
>>
>> Couldn't we "split" the m68k backend in three parts instead?
>> A core part (m68k) containing all common code and two backends
>> based on it: m680x0 and coldfire. (CPU32 would stay with the
>> 68000 of course).
>>
>> This would require slightly more work initially, but it would
>> reduce maintenance costs in the long term.
>>
>
>I have been following this and want to make sure I am understanding.
>
>Would there now be separate m68k and coldfire targets? Said another
>way, would m68k-XYZ be able to include Coldfire support?
The suggestion as I put it forth would be no. You have sepperate
tools, one --target=m68k-xyz for the m68k family, and
--target=coldfire-xyz for the ColdFire family.
--
Peter Barada
peter@the-baradas.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 20:57 ` Peter Barada
@ 2004-12-14 21:41 ` Joel Sherrill <joel@OARcorp.com>
2004-12-14 22:12 ` Peter Barada
0 siblings, 1 reply; 19+ messages in thread
From: Joel Sherrill <joel@OARcorp.com> @ 2004-12-14 21:41 UTC (permalink / raw)
To: Peter Barada; +Cc: bernie, cjaiprakash, gcc, schwab
>>Would there now be separate m68k and coldfire targets? Said another
>>way, would m68k-XYZ be able to include Coldfire support?
>
>
> The suggestion as I put it forth would be no. You have sepperate
> tools, one --target=m68k-xyz for the m68k family, and
> --target=coldfire-xyz for the ColdFire family.
Obviously this has impact beyond gcc and would have to be
coordinated. Targets would have to be added to at least
binutils, gdb, and newlib.
If a decision is made to move on this, I would suggest
that a push is made to get the targets into the other
tools soon so official releases with coldfire-xyz
have a chance to show up before they are requred by gcc.
I would also suggest that we consider being generous
with multilibs on both targets. It looks like
m68k-rtems would only be able to go down 1 multilib
(m5200 based upon 3.3.5) while coldfire could be
expanded to have omre optimal libraries for some
variants.
Personally I don't have a problem with coldfire targets
not defining m68k although it will take a while to get
all the software fixed. As someone said earlier,
embedded developers are cautious and the gcc adoption
timeframe is longer than with Linux distributions.
I would be surprised if it didn't take years to see
all the impacts of not defining m68k. How many
embedded developers are still using gcc 2.95?
--joel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 21:41 ` Joel Sherrill <joel@OARcorp.com>
@ 2004-12-14 22:12 ` Peter Barada
0 siblings, 0 replies; 19+ messages in thread
From: Peter Barada @ 2004-12-14 22:12 UTC (permalink / raw)
To: joel.sherrill; +Cc: bernie, cjaiprakash, gcc, schwab
>>>Would there now be separate m68k and coldfire targets? Said another
>>>way, would m68k-XYZ be able to include Coldfire support?
>>
>>
>> The suggestion as I put it forth would be no. You have sepperate
>> tools, one --target=m68k-xyz for the m68k family, and
>> --target=coldfire-xyz for the ColdFire family.
>
>Obviously this has impact beyond gcc and would have to be
>coordinated. Targets would have to be added to at least
>binutils, gdb, and newlib.
>
>If a decision is made to move on this, I would suggest
>that a push is made to get the targets into the other
>tools soon so official releases with coldfire-xyz
>have a chance to show up before they are requred by gcc.
Yet another part I hand't thought of yet...
I agree that we would have to make patches to binutils and newlib to
support the coldfire-xyz targets and have those go through at least
one release cycle *before* splitting ColdFire off from the m68k backend.
>I would also suggest that we consider being generous
>with multilibs on both targets. It looks like
>m68k-rtems would only be able to go down 1 multilib
>(m5200 based upon 3.3.5) while coldfire could be
>expanded to have omre optimal libraries for some
>variants.
>
>Personally I don't have a problem with coldfire targets
>not defining m68k although it will take a while to get
>all the software fixed. As someone said earlier,
>embedded developers are cautious and the gcc adoption
>timeframe is longer than with Linux distributions.
>I would be surprised if it didn't take years to see
>all the impacts of not defining m68k. How many
>embedded developers are still using gcc 2.95?
We could leave the current m68k definitions in place for
--target=coldfire-xyz for a few revs with the indication that it will
be removed.
I don't expect this to be in gcc within the next *year*, butunless the
issue is rasied now, decided on, and put on the development plan for
the m68k target, it will never get addressed and we end up with even
more software keying off of m68k definitions for ColdFire support.
--
Peter Barada
peter@the-baradas.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-14 8:26 ` Bernardo Innocenti
2004-12-14 14:24 ` Peter Barada
@ 2004-12-17 14:10 ` Gunther Nikl
2004-12-17 14:30 ` Peter Barada
1 sibling, 1 reply; 19+ messages in thread
From: Gunther Nikl @ 2004-12-17 14:10 UTC (permalink / raw)
To: Bernardo Innocenti; +Cc: Peter Barada, cjaiprakash, gcc, schwab
On Tue, Dec 14, 2004 at 09:25:19AM +0100, Bernardo Innocenti wrote:
> >Your probably right, but the quicker that they are seen teh quicker
> >they can be revamped into something acceptable to the mainline.
>
> I'm also a fan of "release early, release often" and
> "many eyes make all bugs shallow" (Linus).
I don't think that you should apply this to a compiler. You will get
big problems if your released compiler has ABI bugs. Fixing those
might be difficult.
Gunther
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-17 14:10 ` Gunther Nikl
@ 2004-12-17 14:30 ` Peter Barada
2004-12-19 0:14 ` Richard Henderson
0 siblings, 1 reply; 19+ messages in thread
From: Peter Barada @ 2004-12-17 14:30 UTC (permalink / raw)
To: gni; +Cc: bernie, cjaiprakash, gcc, schwab
>> >Your probably right, but the quicker that they are seen teh quicker
>> >they can be revamped into something acceptable to the mainline.
>>
>> I'm also a fan of "release early, release often" and
>> "many eyes make all bugs shallow" (Linus).
>
> I don't think that you should apply this to a compiler. You will get
> big problems if your released compiler has ABI bugs. Fixing those
> might be difficult.
The changes we're talking about do not affect the ABI, and are
local to the m68k/coldfire backend(except for adding a configuration
selector for --target=coldfire-*.
--
Peter Barada
peter@the-baradas.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: New target for Coldfire v4e?
2004-12-17 14:30 ` Peter Barada
@ 2004-12-19 0:14 ` Richard Henderson
0 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2004-12-19 0:14 UTC (permalink / raw)
To: Peter Barada; +Cc: gni, bernie, cjaiprakash, gcc, schwab
On Fri, Dec 17, 2004 at 09:28:40AM -0500, Peter Barada wrote:
> The changes we're talking about do not affect the ABI, and are
> local to the m68k/coldfire backend(except for adding a configuration
> selector for --target=coldfire-*.
What do you hope to gain by splitting coldfire out?
Yes, the m68k port could stand to be rewritten from scratch, but
it seems to me that the differential in difficulty between writing
a new port for coldfire and a new port for m68k+coldfire is small.
r~
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: New target for Coldfire v4e?
@ 2004-12-14 7:16 C Jaiprakash, Noida
0 siblings, 0 replies; 19+ messages in thread
From: C Jaiprakash, Noida @ 2004-12-14 7:16 UTC (permalink / raw)
To: Bernardo Innocenti, Peter Barada; +Cc: gcc, schwab
[-- Attachment #1: Type: text/plain, Size: 867 bytes --]
Hi,
> C Jaiprakash, could you please send us your patches for
> a first look? No need to polish them up...
I am sending patches against gcc 3.4.0 release for initial review. I had to
make some changes in elf32-m68k.c for PLT entries so that these entries are
valid for coldfire v4e. Though these changes (elf32-m68k.c) will affect m68k
targets I have to look for better way to do this so that it won't affect
other targets. But these changes are tested. FreeScale has released linux
2.14.x built using gcc 3.4 toolchainn (with these patches)
Thanks and best regards,
C Jaiprakash
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Contributing to the World by creating indispensable value !
System Software CoE @ HCLT-Noida
http://www.hcltechnologies.com
Ph. : +91-120-2510701/702 Ext : 3170
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[-- Attachment #2: config.gcc_patch --]
[-- Type: application/octet-stream, Size: 514 bytes --]
--- ../gcc_cvs/gcc/gcc/config.gcc 2004-04-17 07:58:24.000000000 +0530
+++ ../gcc-3.4.0/gcc/config.gcc 2004-10-04 17:33:54.000000000 +0530
@@ -1437,7 +1437,7 @@
# aka the GNU/Linux C library 6.
tm_file="m68k/m68k.h dbxelf.h elfos.h svr4.h linux.h m68k/linux.h"
tm_defines="MOTOROLA USE_GAS"
- tmake_file="t-slibgcc-elf-ver t-linux"
+ tmake_file="t-slibgcc-elf-ver m68k/t-linux"
# if not configured with --enable-sjlj-exceptions, bump the
# libgcc version number
if test x$sjlj != x1; then
[-- Attachment #3: elf32-m68k.c_patch --]
[-- Type: application/octet-stream, Size: 3727 bytes --]
--- elf32-m68k.c 2004-12-14 12:27:51.000000000 +0530
+++ ../gcc-3.4.0/bfd/elf32-m68k.c 2004-10-04 16:59:08.000000000 +0530
@@ -191,11 +191,11 @@
/* The size in bytes of an entry in the procedure linkage table. */
-#define PLT_ENTRY_SIZE 20
+#define PLT_ENTRY_SIZE 24
/* The first entry in a procedure linkage table looks like this. See
the SVR4 ABI m68k supplement to see how this works. */
-
+#if 0 /* HCLT */
static const bfd_byte elf_m68k_plt0_entry[PLT_ENTRY_SIZE] =
{
0x2f, 0x3b, 0x01, 0x70, /* move.l (%pc,addr),-(%sp) */
@@ -216,6 +216,34 @@
0x60, 0xff, /* bra.l .plt */
0, 0, 0, 0 /* replaced with offset to start of .plt. */
};
+#endif
+
+static const bfd_byte elf_m68k_plt0_entry[PLT_ENTRY_SIZE] =
+{
+ 0x20, 0x3c,
+ 0, 0, 0, 0, /* replaced with offset to .got + 4. */
+ 0x2f, 0x3b, 0x08, 0xfa, /* move.l (%pc,addr),-(%sp) */
+ 0x20, 0x3c,
+ 0, 0, 0, 0, /* replaced with offset to .got + 8. */
+ 0x20, 0x7b, 0x08, 0x00, /* move.l (%pc,%d0:l), %a0 */
+ 0x4e, 0xd0, /* jmp (%a0) */
+ 0x4e, 0x71
+};
+
+/* Subsequent entries in a procedure linkage table look like this. */
+
+static const bfd_byte elf_m68k_plt_entry[PLT_ENTRY_SIZE] =
+{
+ 0x20, 0x3c,
+ 0, 0, 0, 0, /* replaced with offset to symbol's .got entry. */
+ 0x20, 0x7b, 0x08, 0x00, /* move.l (%pc,%d0:l), %a0 */
+ 0x4e, 0xd0, /* jmp (%a0) */
+ 0x2f, 0x3c, /* move.l #offset,-(%sp) */
+ 0, 0, 0, 0, /* replaced with offset into relocation table. */
+ 0x60, 0xff, /* bra.l .plt */
+ 0, 0, 0, 0 /* replaced with offset to start of .plt. */
+};
+
#define CPU32_FLAG(abfd) (elf_elfheader (abfd)->e_flags & EF_CPU32)
@@ -1820,9 +1848,14 @@
/* Fill in the entry in the procedure linkage table. */
memcpy (splt->contents + h->plt.offset, elf_m68k_plt_entry,
PLT_ENTRY_SIZE);
+#if 0 /* HCLT */
plt_off1 = 4;
plt_off2 = 10;
plt_off3 = 16;
+#endif
+ plt_off1 = 2;
+ plt_off2 = 14;
+ plt_off3 = 20;
}
/* The offset is relative to the first extension word. */
@@ -1831,7 +1864,7 @@
+ sgot->output_offset
+ got_offset
- (splt->output_section->vma
- + h->plt.offset + 2)),
+ + h->plt.offset + 2) - 6 ),
splt->contents + h->plt.offset + plt_off1);
bfd_put_32 (output_bfd, plt_index * sizeof (Elf32_External_Rela),
@@ -1844,7 +1877,7 @@
(splt->output_section->vma
+ splt->output_offset
+ h->plt.offset
- + 8),
+ + 12),
sgot->contents + got_offset);
/* Fill in the entry in the .rela.plt section. */
@@ -2033,6 +2066,7 @@
if (!CPU32_FLAG (output_bfd))
{
memcpy (splt->contents, elf_m68k_plt0_entry, PLT_ENTRY_SIZE);
+#if 0 /* HCLT */
bfd_put_32 (output_bfd,
(sgot->output_section->vma
+ sgot->output_offset + 4
@@ -2043,6 +2077,17 @@
+ sgot->output_offset + 8
- (splt->output_section->vma + 10)),
splt->contents + 12);
+#endif
+ bfd_put_32 (output_bfd,
+ (sgot->output_section->vma
+ + sgot->output_offset + 4
+ - (splt->output_section->vma + 2)),
+ splt->contents + 2);
+ bfd_put_32 (output_bfd,
+ (sgot->output_section->vma
+ + sgot->output_offset + 8
+ - (splt->output_section->vma + 10) - 8 ),
+ splt->contents + 12);
elf_section_data (splt->output_section)->this_hdr.sh_entsize
= PLT_ENTRY_SIZE;
}
[-- Attachment #4: lb1sf68.asm_patch --]
[-- Type: application/octet-stream, Size: 7733 bytes --]
--- ../gcc_cvs/gcc/gcc/config/m68k/lb1sf68.asm 2003-10-11 19:52:54.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/lb1sf68.asm 2004-11-04 14:43:30.000000000 +0530
@@ -358,6 +358,7 @@
1: moveml sp@+,d2-d7 | restore data registers
#else
1: moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -687,6 +688,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@- | 3 lines added HCLT
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5
+ lea (-6,pc,a5),a5
#endif
movel a6@(8),d0 | get first operand
movel a6@(12),d1 |
@@ -1244,6 +1248,7 @@
moveml sp@+,d2-d7 | restore data registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -1266,6 +1271,7 @@
moveml sp@+,d2-d7 | restore data registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -1325,6 +1331,7 @@
moveml sp@+,d2-d7
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -1405,6 +1412,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@-
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5 | 2 lines added HCLT
+ lea (-6,pc,a5),a5
#endif
movel a6@(8),d0 | get a into d0-d1
movel a6@(12),d1 |
@@ -1686,6 +1696,7 @@
moveml sp@+,d2-d7
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -1737,6 +1748,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@-
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5 | 2 lines added HCLT
+ lea (-6,pc,a5),a5
#endif
movel a6@(8),d0 | get a into d0-d1
movel a6@(12),d1 |
@@ -1971,6 +1985,7 @@
moveml sp@+,d2-d7 |
#else
moveml sp@,d2-d7 |
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -2160,6 +2175,7 @@
moveml sp@+,d2-d7
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -2178,6 +2194,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@-
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5 | 2 lines added HCLT
+ lea (-6,pc,a5),a5
#endif
movew IMM (NEGATE),d5
movel a6@(8),d0 | get number to negate in d0-d1
@@ -2202,6 +2221,7 @@
moveml sp@+,d2-d7
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -2226,6 +2246,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@-
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5 | 2 lines added HCLT
+ lea (-6,pc,a5),a5
#endif
movew IMM (COMPARE),d5
movel a6@(8),d0 | get first operand
@@ -2291,6 +2314,7 @@
moveml sp@+,d2-d7 | put back the registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -2302,6 +2326,7 @@
moveml sp@+,d2-d7 | put back the registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -2313,6 +2338,7 @@
moveml sp@+,d2-d7 | put back the registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -2567,6 +2593,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@- | 3 lines added HCLT
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5
+ lea (-6,pc,a5),a5
#endif
movel a6@(8),d0 | get first operand
movel a6@(12),d1 | get second operand
@@ -2910,6 +2939,7 @@
moveml sp@+,d2-d7 | restore data registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -2924,6 +2954,7 @@
moveml sp@+,d2-d7 | restore data registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -2982,6 +3013,7 @@
moveml sp@+,d2-d7 | restore data registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -3051,6 +3083,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@- | 3 lines added HCLT
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5
+ lea (-6,pc,a5),a5
#endif
movel a6@(8),d0 | get a into d0
movel a6@(12),d1 | and b into d1
@@ -3217,6 +3252,7 @@
moveml sp@+,d2-d7 |
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -3265,6 +3301,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@- | 3 lines added HCLT
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5
+ lea (-6,pc,a5),a5
#endif
movel a6@(8),d0 | get a into d0
movel a6@(12),d1 | and b into d1
@@ -3417,6 +3456,7 @@
moveml sp@+,d2-d7 |
#else
moveml sp@,d2-d7 |
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -3569,6 +3609,7 @@
moveml sp@+,d2-d7
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -3590,6 +3631,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@- | 3 lines added HCLT
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5
+ lea (-6,pc,a5),a5
#endif
movew IMM (NEGATE),d5
movel a6@(8),d0 | get number to negate in d0
@@ -3610,6 +3654,7 @@
moveml sp@+,d2-d7
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -3634,6 +3679,9 @@
#else
link a6,IMM (-24)
moveml d2-d7,sp@
+ movel a5, sp@-
+ movel #_GLOBAL_OFFSET_TABLE_@GOTPC, a5 | 2 lines added HCLT
+ lea (-6,pc,a5),a5
#endif
movew IMM (COMPARE),d5
movel a6@(8),d0 | get first operand
@@ -3684,6 +3732,7 @@
moveml sp@+,d2-d7 | put back the registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
#endif
unlk a6
rts
@@ -3693,6 +3742,7 @@
moveml sp@+,d2-d7 | put back the registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
@@ -3704,6 +3754,7 @@
moveml sp@+,d2-d7 | put back the registers
#else
moveml sp@,d2-d7
+ moveal a6@(-28), a5 | 1 line added HCLT
| XXX if frame pointer is ever removed, stack pointer must
| be adjusted here.
#endif
[-- Attachment #5: linux.h_patch --]
[-- Type: application/octet-stream, Size: 2819 bytes --]
--- ../gcc_cvs/gcc/gcc/config/m68k/linux.h 2003-11-29 08:38:11.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/linux.h 2004-10-14 19:28:15.000000000 +0530
@@ -83,15 +83,39 @@
#define WCHAR_TYPE_SIZE BITS_PER_WORD
/* Target OS builtins. */
+
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
LINUX_TARGET_OS_CPP_BUILTINS(); \
- builtin_define_std ("mc68000"); \
- builtin_define_std ("mc68020"); \
+ if ( TARGET_CFV4E ) \
+ { \
+ builtin_define_std ("mcfv4e"); \
+ } \
+ else \
+ { \
+ builtin_define_std ("mc68000"); \
+ builtin_define_std ("mc68020"); \
+ } \
} \
while (0)
-
+/*
+#define TARGET_OS_CPP_BUILTINS() \
+ do \
+ { \
+ LINUX_TARGET_OS_CPP_BUILTINS(); \
+ builtin_define_std ("mc68000"); \
+ builtin_define_std ("mc68020"); \
+ } \
+ while (0)
+#define TARGET_OS_CPP_BUILTINS() \
+ do \
+ { \
+ LINUX_TARGET_OS_CPP_BUILTINS(); \
+ builtin_define_std ("mcfv4e"); \
+ } \
+ while (0)
+*/
#define TARGET_OBJFMT_CPP_BUILTINS() \
do \
{ \
@@ -102,18 +126,20 @@
#undef CPP_SPEC
#if TARGET_DEFAULT & MASK_68881
#define CPP_SPEC \
- "%{fPIC|fpic|fPIE|fpie:-D__PIC__ -D__pic__} %{!msoft-float:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
+"%{m68020:-Dmc68020 -D__mc68020__ %{!msoft-float:-D__HAVE_68881 }}%{mcfv4e:-D__mcoldfire__ -Dmcoldfire -D__HAVE_FPU__ }%{mcfv4:-D__mcoldfire__ -Dmcoldfire }%{!m68020:%{!mcfv4:%{!mcfv4e:-D__mcoldfire__ -Dmcoldfire -D__HAVE_FPU__ }}}%{fPIC: -D__PIC__ -D__pic__ }%{fpic: -D__PIC__ -D__pic__ }%{posix:-D_POSIX_SOURCE }"
#else
#define CPP_SPEC \
- "%{fPIC|fpic|fPIE|fpie:-D__PIC__ -D__pic__} %{m68881:-D__HAVE_68881__} %{posix:-D_POSIX_SOURCE} %{pthread:-D_REENTRANT}"
+ "%{fPIC|fpic|fPIE|fpie:-D__PIC__ -D__pic__ } %{m68881:-D__HAVE_68881__ } %{posix:-D_POSIX_SOURCE } %{pthread:-D_REENTRANT }"
#endif
+
+
/* We override the ASM_SPEC from svr4.h because we must pass -m68040 down
to the assembler. */
#undef ASM_SPEC
#define ASM_SPEC \
"%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
-%{m68040} %{m68060:-m68040}"
+%{m68040} %{m68060:-m68040} %{mcfv4e} "
/* Provide a LINK_SPEC appropriate for GNU/Linux. Here we provide support
for the special GCC options -static and -shared, which allow us to
[-- Attachment #6: m68k.c_patch --]
[-- Type: application/octet-stream, Size: 35060 bytes --]
--- ../gcc_cvs/gcc/gcc/config/m68k/m68k.c 2004-10-06 22:36:49.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/m68k.c 2004-12-14 11:53:23.000000000 +0530
@@ -150,6 +150,7 @@
sCC expanders peek at this to determine what to do for the
68060, which has no fsCC instructions. */
int m68k_last_compare_had_fp_operands;
+static void cfv4e_encode_section_info (tree, rtx, int);
\f
/* Initialize the GCC target structure. */
@@ -204,6 +205,10 @@
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
+#undef TARGET_ENCODE_SECTION_INFO
+#define TARGET_ENCODE_SECTION_INFO cfv4e_encode_section_info
+
+
static const struct attribute_spec m68k_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
@@ -211,8 +216,11 @@
{ NULL, 0, 0, false, false, false, NULL }
};
+/* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
+static char internal_label_prefix[16];
+static int internal_label_prefix_len;
+
struct gcc_target targetm = TARGET_INITIALIZER;
-\f
/* Sometimes certain combinations of command options do not make
sense on a particular target machine. You can define a macro
`OVERRIDE_OPTIONS' to take account of this. This macro, if
@@ -298,8 +306,8 @@
/* -fPIC uses 32-bit pc-relative displacements, which don't exist
until the 68020. */
- if (!TARGET_68020 && !TARGET_COLDFIRE && (flag_pic == 2))
- error("-fPIC is not currently supported on the 68000 or 68010\n");
+ if (!TARGET_68020 && !TARGET_COLDFIRE && (flag_pic == 2) )
+ error("-fPIC is not currently supported on the 68000 or 68010 \n");
/* ??? A historic way of turning on pic, or is this intended to
be an embedded thing that doesn't have the same name binding
@@ -314,6 +322,14 @@
avoid when we are doing PIC on svr4 m68k. */
if (flag_pic)
flag_no_function_cse = 1;
+ /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
+ {
+ char *p;
+ ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
+ p = strchr (internal_label_prefix, 'X');
+ internal_label_prefix_len = p - internal_label_prefix;
+ *p = '\0';
+ }
SUBTARGET_OVERRIDE_OPTIONS;
}
@@ -380,7 +396,7 @@
current_frame.foffset = 0;
mask = rmask = saved = 0;
- if (TARGET_68881 /* || TARGET_CFV4E */)
+ if (TARGET_68881 || TARGET_CFV4E )
{
for (regno = 16; regno < 24; regno++)
if (m68k_save_reg (regno, interrupt_handler))
@@ -389,7 +405,7 @@
rmask |= 1 << (23 - regno);
saved++;
}
- current_frame.foffset = saved * 12 /* (TARGET_CFV4E ? 8 : 12) */;
+ current_frame.foffset = saved * (TARGET_CFV4E ? 8 : 12) ;
current_frame.offset += current_frame.foffset;
}
current_frame.fpu_no = saved;
@@ -495,7 +511,10 @@
fsize_with_regs = current_frame.size;
if (TARGET_COLDFIRE && current_frame.reg_no > 2)
fsize_with_regs += current_frame.reg_no * 4;
-
+ /* Currently commented
+ if (TARGET_CFV4E && current_frame.fpu_no > 2)
+ fsize_with_regs += current_frame.fpu_no * 8; */
+
if (frame_pointer_needed)
{
if (current_frame.size == 0 && TARGET_68040)
@@ -570,7 +589,16 @@
if (current_frame.fpu_mask)
{
- asm_fprintf (stream, MOTOROLA ?
+
+ if (TARGET_CFV4E)
+ {
+ asm_fprintf (stream,
+ "\tlea (%wd,%Rsp),%Rsp\n"
+ "\tfmovem %I0x%x,%Rsp@\n",
+ -(current_frame.foffset),current_frame.fpu_mask);
+ }
+ else
+ asm_fprintf (stream, MOTOROLA ?
"\tfmovm %I0x%x,-(%Rsp)\n" :
"\tfmovem %I0x%x,%Rsp@-\n",
current_frame.fpu_mask);
@@ -672,8 +700,21 @@
else
{
if (MOTOROLA)
- asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
- reg_names[PIC_OFFSET_TABLE_REGNUM]);
+ {
+ if (TARGET_CFV4E)
+ {
+ asm_fprintf (stream, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_@GOTPC, %s\n",
+ reg_names[PIC_OFFSET_TABLE_REGNUM]);
+ asm_fprintf (stream, "\tlea (-6,%Rpc,%s),%s\n",
+ reg_names[PIC_OFFSET_TABLE_REGNUM],
+ reg_names[PIC_OFFSET_TABLE_REGNUM]);
+ }
+ else
+ {
+ asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
+ reg_names[PIC_OFFSET_TABLE_REGNUM]);
+ }
+ }
else
{
asm_fprintf (stream, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
@@ -700,6 +741,210 @@
return current_frame.reg_no ? false : true;
}
+/* Return 1 if OP is valid fpu operand */
+int
+fpu_operand (op, mode)
+ register rtx op;
+ enum machine_mode mode;
+{
+ if (TARGET_CFV4E) {
+ if (GET_CODE (op) == CONST_DOUBLE)
+ return 0;
+ }
+ return general_operand (op, mode);
+}
+
+/* Emit insns to move operands[1] into operands[0].
+
+ Return 1 if we have written out everything that needs to be done to
+ do the move. Otherwise, return 0 and the caller will emit the move
+ normally.
+
+ Note SCRATCH_REG may not be in the proper mode depending on how it
+ will be used. This routine is resposible for creating a new copy
+ of SCRATCH_REG in the proper mode. */
+
+int
+emit_move_sequence (operands, mode, scratch_reg)
+ rtx *operands;
+ enum machine_mode mode;
+ rtx scratch_reg;
+{
+ register rtx operand0 = operands[0];
+ register rtx operand1 = operands[1];
+ register rtx tem;
+
+ if (scratch_reg
+ && reload_in_progress && GET_CODE (operand0) == REG
+ && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
+ operand0 = reg_equiv_mem[REGNO (operand0)];
+ else if (scratch_reg
+ && reload_in_progress && GET_CODE (operand0) == SUBREG
+ && GET_CODE (SUBREG_REG (operand0)) == REG
+ && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
+ {
+ /* We must not alter SUBREG_BYTE (operand0) since that would confuse
+ the code which tracks sets/uses for delete_output_reload. */
+ rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
+ reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
+ SUBREG_BYTE (operand0));
+ operand0 = alter_subreg (temp);
+ }
+
+ if (scratch_reg
+ && reload_in_progress && GET_CODE (operand1) == REG
+ && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
+ operand1 = reg_equiv_mem[REGNO (operand1)];
+ else if (scratch_reg
+ && reload_in_progress && GET_CODE (operand1) == SUBREG
+ && GET_CODE (SUBREG_REG (operand1)) == REG
+ && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
+ {
+ /* We must not alter SUBREG_BYTE (operand0) since that would confuse
+ the code which tracks sets/uses for delete_output_reload. */
+ rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
+ reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
+ SUBREG_BYTE (operand1));
+ operand1 = alter_subreg (temp);
+ }
+
+ if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
+ && ((tem = find_replacement (&XEXP (operand0, 0)))
+ != XEXP (operand0, 0)))
+ operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
+ if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
+ && ((tem = find_replacement (&XEXP (operand1, 0)))
+ != XEXP (operand1, 0)))
+ operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
+
+ /* Handle secondary reloads for loads/stores of FP registers where
+ the address is symbolic by using the scratch register */
+ if (fp_reg_operand (operand0, mode)
+ && ((GET_CODE (operand1) == MEM
+ && ! memory_address_p (DFmode, XEXP (operand1, 0)))
+ || ((GET_CODE (operand1) == SUBREG
+ && GET_CODE (XEXP (operand1, 0)) == MEM
+ && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
+ && scratch_reg)
+ {
+ if (GET_CODE (operand1) == SUBREG)
+ operand1 = XEXP (operand1, 0);
+
+ /* SCRATCH_REG will hold an address. We want
+ it in SImode regardless of what mode it was originally given
+ to us. */
+ scratch_reg = force_mode (SImode, scratch_reg);
+
+ /* D might not fit in 14 bits either; for such cases load D into
+ scratch reg. */
+ if (!memory_address_p (Pmode, XEXP (operand1, 0)))
+ {
+ emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
+ emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
+ Pmode,
+ XEXP (XEXP (operand1, 0), 0),
+ scratch_reg));
+ }
+ else
+ emit_move_insn (scratch_reg, XEXP (operand1, 0));
+ emit_insn (gen_rtx_SET (VOIDmode, operand0,
+ gen_rtx_MEM (mode, scratch_reg)));
+ return 1;
+ }
+ else if (fp_reg_operand (operand1, mode)
+ && ((GET_CODE (operand0) == MEM
+ && ! memory_address_p (DFmode, XEXP (operand0, 0)))
+ || ((GET_CODE (operand0) == SUBREG)
+ && GET_CODE (XEXP (operand0, 0)) == MEM
+ && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
+ && scratch_reg)
+ {
+ if (GET_CODE (operand0) == SUBREG)
+ operand0 = XEXP (operand0, 0);
+
+ /* SCRATCH_REG will hold an address and maybe the actual data. We want
+ it in SIMODE regardless of what mode it was originally given
+ to us. */
+ scratch_reg = force_mode (SImode, scratch_reg);
+
+ /* D might not fit in 14 bits either; for such cases load D into
+ scratch reg. */
+ if (!memory_address_p (Pmode, XEXP (operand0, 0)))
+ {
+ emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
+ emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
+ 0)),
+ Pmode,
+ XEXP (XEXP (operand0, 0),
+ 0),
+ scratch_reg));
+ }
+ else
+ emit_move_insn (scratch_reg, XEXP (operand0, 0));
+ emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
+ operand1));
+ return 1;
+ }
+ /* Handle secondary reloads for loads of FP registers from constant
+ expressions by forcing the constant into memory.
+
+ use scratch_reg to hold the address of the memory location.
+
+ The proper fix is to change PREFERRED_RELOAD_CLASS to return
+ NO_REGS when presented with a const_int and an register class
+ containing only FP registers. Doing so unfortunately creates
+ more problems than it solves. Fix this for 2.5. */
+ else if (fp_reg_operand (operand0, mode)
+ && CONSTANT_P (operand1)
+ && scratch_reg)
+ {
+ rtx xoperands[2];
+
+ /* SCRATCH_REG will hold an address and maybe the actual data. We want
+ it in SIMODE regardless of what mode it was originally given
+ to us. */
+ scratch_reg = force_mode (SImode, scratch_reg);
+
+ /* Force the constant into memory and put the address of the
+ memory location into scratch_reg. */
+ xoperands[0] = scratch_reg;
+ xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
+ emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1]));
+
+ /* Now load the destination register. */
+ emit_insn (gen_rtx_SET (mode, operand0,
+ gen_rtx_MEM (mode, scratch_reg)));
+ return 1;
+ }
+
+ /* Now have insn-emit do whatever it normally does. */
+ return 0;
+}
+
+int
+fp_reg_operand (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ return reg_renumber && FP_REG_P (op);
+}
+/* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
+ new rtx with the correct mode. */
+static inline rtx
+force_mode (mode, orig)
+ enum machine_mode mode;
+ rtx orig;
+{
+ if (mode == GET_MODE (orig))
+ return orig;
+
+ if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
+ abort ();
+
+ return gen_rtx_REG (mode, REGNO (orig));
+}
+
+
/* This function generates the assembly code for function exit,
on machines that need it.
@@ -753,6 +998,9 @@
if (TARGET_COLDFIRE && restore_from_sp && (current_frame.reg_no > 2))
fsize_with_regs += current_frame.reg_no * 4;
+ if (TARGET_CFV4E && restore_from_sp && current_frame.fpu_no > 2)
+ fsize_with_regs += current_frame.fpu_no * 8;
+
if (current_frame.offset + fsize >= 0x8000
&& ! restore_from_sp
&& (current_frame.reg_mask || current_frame.fpu_mask))
@@ -773,7 +1021,7 @@
in code size. */
int i;
- HOST_WIDE_INT offset = current_frame.offset + fsize;
+ HOST_WIDE_INT offset = current_frame.offset + fsize;
for (i = 0; i < 16; i++)
if (current_frame.reg_mask & (1 << i))
@@ -815,6 +1063,7 @@
else if (current_frame.reg_mask)
{
/* The ColdFire requires special handling due to its limited moveml insn. */
+ HOST_WIDE_INT offset = current_frame.offset + fsize;
if (TARGET_COLDFIRE)
{
if (big)
@@ -835,13 +1084,13 @@
{
if (MOTOROLA)
asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n",
- current_frame.offset + fsize,
+ offset,
reg_names[FRAME_POINTER_REGNUM],
current_frame.reg_mask);
else
asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n",
reg_names[FRAME_POINTER_REGNUM],
- current_frame.offset + fsize,
+ offset,
current_frame.reg_mask);
}
}
@@ -851,13 +1100,13 @@
{
if (MOTOROLA)
asm_fprintf (stream, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
- current_frame.offset + fsize,
+ offset,
reg_names[FRAME_POINTER_REGNUM],
current_frame.reg_mask);
else
asm_fprintf (stream, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
reg_names[FRAME_POINTER_REGNUM],
- current_frame.offset + fsize,
+ offset,
current_frame.reg_mask);
}
else if (restore_from_sp)
@@ -871,13 +1120,13 @@
{
if (MOTOROLA)
asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n",
- current_frame.offset + fsize,
+ offset,
reg_names[FRAME_POINTER_REGNUM],
current_frame.reg_mask);
else
asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n",
reg_names[FRAME_POINTER_REGNUM],
- current_frame.offset + fsize,
+ offset,
current_frame.reg_mask);
}
}
@@ -886,7 +1135,7 @@
{
if (big)
{
- if (MOTOROLA)
+ if (MOTOROLA && !TARGET_CFV4E)
asm_fprintf (stream, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
current_frame.foffset + fsize,
reg_names[FRAME_POINTER_REGNUM],
@@ -899,16 +1148,24 @@
}
else if (restore_from_sp)
{
- if (MOTOROLA)
- asm_fprintf (stream, "\tfmovm (%Rsp)+,%I0x%x\n",
- current_frame.fpu_rev_mask);
- else
- asm_fprintf (stream, "\tfmovem %Rsp@+,%I0x%x\n",
+ if (TARGET_CFV4E )
+ asm_fprintf (stream,
+ "\taddal %I%wd,%Rsp\n"
+ "\tfmovem %Rsp@, %I0x%x\n",
+ (current_frame.foffset+ fsize ),current_frame.fpu_rev_mask);
+ else
+ {
+ if (MOTOROLA && !TARGET_CFV4E)
+ asm_fprintf (stream, "\tfmovm (%Rsp)+,%I0x%x\n",
current_frame.fpu_rev_mask);
+ else
+ asm_fprintf (stream, "\tfmovem %Rsp@+,%I0x%x\n",
+ current_frame.fpu_rev_mask);
+ }
}
else
{
- if (MOTOROLA)
+ if (MOTOROLA && !TARGET_CFV4E)
asm_fprintf (stream, "\tfmovm -%wd(%s),%I0x%x\n",
current_frame.foffset + fsize,
reg_names[FRAME_POINTER_REGNUM],
@@ -1364,6 +1621,8 @@
bool
symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
+ if ( flag_pic && TARGET_CFV4E)
+ return symbolic_operand_cfv4e(op,mode);
switch (GET_CODE (op))
{
case SYMBOL_REF:
@@ -1386,7 +1645,51 @@
return false;
}
}
-\f
+bool
+symbolic_operand_cfv4e (op, mode)
+ register rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ switch (GET_CODE (op))
+ {
+ case SYMBOL_REF:
+ case LABEL_REF:
+ return true;
+
+ case CONST:
+ op = XEXP (op, 0);
+ if (GET_CODE (op) == SYMBOL_REF
+ || GET_CODE (op) == LABEL_REF
+ || (GET_CODE (op) == UNSPEC
+ && (XINT (op, 1) == UNSPEC_GOT
+ || XINT (op, 1) == UNSPEC_GOTOFF
+ || XINT (op, 1) == 15)))
+ return true;
+ if (GET_CODE (op) != PLUS
+ || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ return false;
+
+ op = XEXP (op, 0);
+ if (GET_CODE (op) == SYMBOL_REF
+ || GET_CODE (op) == LABEL_REF)
+ return true;
+ /* Only @GOTOFF gets offsets. */
+ if (GET_CODE (op) != UNSPEC
+ || XINT (op, 1) != 7)
+ return false;
+
+ op = XVECEXP (op, 0, 0);
+ if (GET_CODE (op) == SYMBOL_REF
+ || GET_CODE (op) == LABEL_REF)
+ return true;
+ return false;
+
+ default:
+ return false;
+ }
+}
+
+
/* Check for sign_extend or zero_extend. Used for bit-count operands. */
int
@@ -1451,6 +1754,10 @@
{
rtx pic_ref = orig;
+ if (TARGET_CFV4E)
+ {
+ return legitimize_pic_cfv4e(orig,mode,reg);
+ }
/* First handle a simple SYMBOL_REF or LABEL_REF */
if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
{
@@ -1494,7 +1801,6 @@
return pic_ref;
}
-\f
typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
static CONST_METHOD const_method (rtx);
@@ -2726,13 +3032,28 @@
}
else if (GET_CODE (op) == MEM)
{
- output_address (XEXP (op, 0));
- if (letter == 'd' && ! TARGET_68020
- && CONSTANT_ADDRESS_P (XEXP (op, 0))
- && !(GET_CODE (XEXP (op, 0)) == CONST_INT
- && INTVAL (XEXP (op, 0)) < 0x8000
- && INTVAL (XEXP (op, 0)) >= -0x8000))
- fprintf (file, MOTOROLA ? ".l" : ":l");
+ if (letter != 'P')
+ {
+ output_address (XEXP (op, 0));
+ if (letter == 'd' && ! TARGET_68020
+ && CONSTANT_ADDRESS_P (XEXP (op, 0))
+ && !(GET_CODE (XEXP (op, 0)) == CONST_INT
+ && INTVAL (XEXP (op, 0)) < 0x8000
+ && INTVAL (XEXP (op, 0)) >= -0x8000))
+ fprintf (file, MOTOROLA ? ".l" : ":l");
+ }
+ else
+ {
+ op = XEXP (op, 0);
+ if (flag_pic && CONSTANT_ADDRESS_P (op))
+ output_pic_addr_const (file, op, letter);
+ else if (CONSTANT_ADDRESS_P (op) && letter == 'P'
+ && GET_CODE (op) != CONST_INT)
+ output_addr_const (file, op);
+ else
+ output_address(op);
+ }
+
}
else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
{
@@ -2754,14 +3075,28 @@
}
else
{
- /* Use `print_operand_address' instead of `output_addr_const'
- to ensure that we print relevant PIC stuff. */
- asm_fprintf (file, "%I");
- if (TARGET_PCREL
- && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
- print_operand_address (file, op);
+ if (letter != 'P')
+ {
+
+ /* Use `print_operand_address' instead of `output_addr_const'
+ to ensure that we print relevant PIC stuff. */
+
+ asm_fprintf (file, "%I");
+ if (TARGET_PCREL
+ && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
+ print_operand_address (file, op);
+ else
+ output_addr_const (file, op);
+ }
else
- output_addr_const (file, op);
+ {
+ if (GET_CODE (op) == CONST_INT)
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
+ else if (flag_pic)
+ output_pic_addr_const (file, op, letter);
+ else
+ output_addr_const (file, op);
+ }
}
}
@@ -3247,6 +3582,10 @@
|| GET_CODE (XEXP (op, 0)) == LABEL_REF
|| GET_CODE (XEXP (op, 0)) == CONST))
return 1;
+ /* Accept PIC symols */
+ if (TARGET_CFV4E && flag_pic && symbolic_pic_operand(op, mode))
+ return 1;
+
return general_operand (op, mode);
}
@@ -3508,3 +3847,464 @@
output_asm_insn (fmt, xops);
}
+
+
+/* PIC additions for CFV4E */
+int
+legitimate_pic_operand_p (op)
+ rtx op;
+{
+ if (!SYMBOLIC_CONST (op))
+ return 1;
+ return legitimate_pic_address_disp_p (op);
+}
+/* Determine if a given CONST RTX is a valid memory displacement
+ in PIC mode. */
+
+int
+legitimate_pic_address_disp_p (disp)
+ register rtx disp;
+{
+ if (GET_CODE (disp) != CONST)
+ return 0;
+ disp = XEXP (disp, 0);
+
+ if (GET_CODE (disp) == PLUS)
+ {
+ if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
+ return 0;
+ disp = XEXP (disp, 0);
+ }
+
+ if (GET_CODE (disp) != UNSPEC
+ || XVECLEN (disp, 0) != 1)
+ return 0;
+
+ /* Must be @GOT or @GOTOFF. */
+ switch (XINT (disp, 1))
+ {
+ case 6: /* @GOT */
+ return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
+
+ case 7: /* @GOTOFF */
+ return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
+ }
+
+ return 0;
+}
+
+/* Returns 1 if OP contains a symbol reference */
+
+int
+symbolic_reference_mentioned_p (op)
+ rtx op;
+{
+ register const char *fmt;
+ register int i;
+
+ if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
+ return 1;
+
+ fmt = GET_RTX_FORMAT (GET_CODE (op));
+ for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
+ {
+ if (fmt[i] == 'E')
+ {
+ register int j;
+
+ for (j = XVECLEN (op, i) - 1; j >= 0; j--)
+ if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
+ return 1;
+ }
+
+ else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Return true if OP is a symbolic operand that resolves locally. */
+
+static int local_symbolic_operand PARAMS ((rtx, enum machine_mode));
+static int
+local_symbolic_operand (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ if (GET_CODE (op) == LABEL_REF)
+ return 1;
+
+#if 0 /* HCLT : This creates problems for static const char *const x = "XXX" + 2 */
+ if (GET_CODE (op) == CONST
+ && GET_CODE (XEXP (op, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+ op = XEXP (XEXP (op, 0), 0);
+#endif
+
+ if (GET_CODE (op) != SYMBOL_REF)
+ return 0;
+
+#if 1
+ /* These we've been told are local by varasm and encode_section_info
+ respectively. */
+ if (CONSTANT_POOL_ADDRESS_P (op) || SYMBOL_REF_FLAG (op))
+ return 1;
+
+ /* There is, however, a not insubstantial body of code in the rest of
+ the compiler that assumes it can just stick the results of
+ ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
+ /* ??? This is a hack. Should update the body of the compiler to
+ always create a DECL an invoke ENCODE_SECTION_INFO. */
+ if (strncmp (XSTR (op, 0), internal_label_prefix,
+ internal_label_prefix_len) == 0)
+ return 1;
+#endif
+
+ return 0;
+}
+
+void
+m68k_expand_move (mode, operands)
+ enum machine_mode mode;
+ rtx operands[];
+{
+ int strict = (reload_in_progress || reload_completed);
+ rtx insn;
+
+ if (flag_pic && mode == Pmode && symbolic_operand (operands[1], Pmode))
+ {
+ /* Emit insns to move operands[1] into operands[0]. */
+
+ if (GET_CODE (operands[0]) == MEM)
+ operands[1] = force_reg (Pmode, operands[1]);
+ else
+ {
+ rtx temp = operands[0];
+ if (GET_CODE (temp) != REG)
+ temp = gen_reg_rtx (Pmode);
+ temp = legitimize_pic_address (operands[1], SImode, temp);
+ if (temp == operands[0])
+ return;
+ operands[1] = temp;
+ }
+ }
+ else
+ {
+ if (GET_CODE (operands[0]) == MEM
+ && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
+ || !push_operand (operands[0], mode))
+ && GET_CODE (operands[1]) == MEM)
+ operands[1] = force_reg (mode, operands[1]);
+
+ if (push_operand (operands[0], mode)
+ && ! general_no_elim_operand (operands[1], mode))
+ operands[1] = copy_to_mode_reg (mode, operands[1]);
+
+ if (FLOAT_MODE_P (mode))
+ {
+ /* If we are loading a floating point constant to a register,
+ force the value to memory now, since we'll get better code
+ out the back end. */
+#if 1
+ if (strict)
+ ;
+ else if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ operands[1] = validize_mem (force_const_mem (mode, operands[1]));
+#else
+ if (strict)
+ ;
+ else if (GET_CODE (operands[1]) == CONST_DOUBLE
+ && register_operand (operands[0], mode))
+ operands[1] = validize_mem (force_const_mem (mode, operands[1]));
+#endif
+ }
+ }
+
+ insn = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
+
+ emit_insn (insn);
+}
+
+
+int
+general_no_elim_operand (op, mode)
+ register rtx op;
+ enum machine_mode mode;
+{
+ rtx t = op;
+ if (GET_CODE (t) == SUBREG)
+ t = SUBREG_REG (t);
+ if (t == arg_pointer_rtx || t == frame_pointer_rtx
+ || t == virtual_incoming_args_rtx || t == virtual_stack_vars_rtx
+ || t == virtual_stack_dynamic_rtx)
+ return 0;
+ if (REG_P (t)
+ && REGNO (t) >= FIRST_VIRTUAL_REGISTER
+ && REGNO (t) <= LAST_VIRTUAL_REGISTER)
+ return 0;
+
+ return general_operand (op, mode);
+}
+
+int
+constant_call_address_operand (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ if (GET_CODE (op) == CONST
+ && GET_CODE (XEXP (op, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+ op = XEXP (XEXP (op, 0), 0);
+ return (GET_CODE (op) == SYMBOL_REF || GET_CODE(op) == REG );
+}
+
+/* Test for a valid operand for a call instruction. Don't allow the
+ arg pointer register or virtual regs since they may decay into
+ reg + const, which the patterns can't handle. */
+
+int
+call_insn_operand (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ /* Disallow indirect through a virtual register. This leads to
+ compiler aborts when trying to eliminate them. */
+ if (GET_CODE (op) == REG
+ && (op == arg_pointer_rtx
+ || op == frame_pointer_rtx
+ || (REGNO (op) >= FIRST_PSEUDO_REGISTER
+ && REGNO (op) <= LAST_VIRTUAL_REGISTER)))
+ return 0;
+
+ /* Disallow `call 1234'. Due to varying assembler lameness this
+ gets either rejected or translated to `call .+1234'. */
+ if (GET_CODE (op) == CONST_INT)
+ return 0;
+
+#if 1
+ /* Explicitly allow SYMBOL_REF even if pic. */
+ if (GET_CODE (op) == SYMBOL_REF)
+ return 1;
+#endif
+
+#if 0
+ /* Half-pic doesn't allow anything but registers and constants.
+ We've just taken care of the later. */
+ if (HALF_PIC_P ())
+ return register_operand (op, Pmode);
+#endif
+
+ /* Otherwise we can allow any general_operand in the address. */
+ return general_operand (op, Pmode);
+}
+
+static void output_pic_addr_const PARAMS ((FILE *, rtx, int));
+static void output_pic_addr_const(file, op, code)
+ FILE *file;
+ rtx op;
+ int code;
+{
+ if (GET_CODE (op) == CONST)
+ op = XEXP(op, 0);
+ if (GET_CODE (op) == UNSPEC)
+ {
+ if (XVECLEN (op, 0) != 1)
+ abort ();
+ output_pic_addr_const (file, XVECEXP (op, 0, 0), '\0');
+ switch (XINT (op, 1))
+ {
+ case UNSPEC_PIC:
+ break; /* nothing to do... */
+ case UNSPEC_GOT:
+ fputs ("@GOT", file);
+ break;
+ case UNSPEC_GOTOFF:
+ fputs ("@GOTOFF", file);
+ break;
+ case UNSPEC_PLT:
+ fputs ("@PLT", file);
+ break;
+ case 15:
+ fputs ("@GOTPCREL(%RIP)", file);
+ break;
+ default:
+ output_operand_lossage ("invalid UNSPEC as operand");
+ break;
+ }
+ }
+ else
+ output_addr_const(file, op);
+}
+
+static int symbolic_pic_operand(op, mode)
+ rtx op;
+ enum machine_mode mode;
+{
+ if (GET_CODE(op) != CONST)
+ return 0;
+ op = XEXP (op, 0);
+ if (GET_CODE (op) == SYMBOL_REF
+ || GET_CODE (op) == LABEL_REF
+ || (GET_CODE (op) == UNSPEC
+ && (XINT (op, 1) == UNSPEC_GOT
+ || XINT (op, 1) == UNSPEC_GOTOFF
+ || XINT (op, 1) == UNSPEC_PIC
+ || XINT (op, 1) == 15) ))
+ return 1;
+ return 0;
+}
+
+rtx
+legitimize_pic_cfv4e(orig, mode, reg)
+ rtx orig, reg;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ rtx addr = orig;
+ rtx pic_ref = addr;
+ rtx base;
+
+ /* First handle a simple SYMBOL_REF or LABEL_REF */
+ if (local_symbolic_operand(addr, Pmode))
+ {
+ if (reg == 0)
+ reg = gen_reg_rtx (Pmode);
+ if (reg == 0)
+ abort ();
+
+ pic_ref = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_PIC);
+ pic_ref = gen_rtx_CONST (Pmode, pic_ref);
+ /* Now move the symbol into a register(w/o using emit_move_insn) */
+ emit_insn (gen_rtx_SET (Pmode, reg, pic_ref));
+ pic_ref = gen_rtx_MEM (Pmode,
+ gen_rtx_PLUS (Pmode,
+ pic_offset_table_rtx, reg));
+ RTX_UNCHANGING_P (pic_ref) = 1;
+ current_function_uses_pic_offset_table = 1;
+ emit_move_insn (reg, pic_ref);
+ return reg;
+ }
+ else if (GET_CODE (addr) == SYMBOL_REF)
+ {
+ /* This symbol must be referenced via a load from the
+ Global Offset Table (@GOT). */
+
+ current_function_uses_pic_offset_table = 1;
+ pic_ref = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
+ pic_ref = gen_rtx_CONST (Pmode, pic_ref);
+ pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, pic_ref);
+ pic_ref = gen_rtx_MEM (Pmode, pic_ref);
+ RTX_UNCHANGING_P (pic_ref) = 1;
+ set_mem_alias_set (pic_ref, m68k_GOT_alias_set ());
+
+ if (reg == 0)
+ reg = gen_reg_rtx (Pmode);
+ emit_move_insn (reg, pic_ref);
+ pic_ref = reg;
+ }
+ else
+ {
+ if (GET_CODE (addr) == CONST)
+ {
+ addr = XEXP (addr, 0);
+
+ /* We must match stuff we generate before. Assume the only
+ unspecs that can get here are ours. Not that we could do
+ anything with them anyway... */
+ if (GET_CODE (addr) == UNSPEC)
+ return orig;
+ if ((GET_CODE (addr) == PLUS
+ && GET_CODE (XEXP (addr, 0)) == UNSPEC))
+ return addr;
+ if (GET_CODE (addr) != PLUS)
+ abort ();
+ }
+ if (GET_CODE (addr) == PLUS)
+ {
+ rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
+
+ /* Check first to see if this is a constant offset from a @GOTOFF
+ symbol reference.
+ if (local_symbolic_operand (op0, Pmode)
+ && GET_CODE (op1) == CONST_INT)
+ {
+ current_function_uses_pic_offset_table = 1;
+ pic_ref = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), UNSPEC_GOTOFF);
+ pic_ref = gen_rtx_PLUS (Pmode, pic_ref, op1);
+ pic_ref = gen_rtx_CONST (Pmode, pic_ref);
+ pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, pic_ref);
+
+ if (reg != 0)
+ {
+ emit_move_insn (reg, pic_ref);
+ pic_ref = reg;
+ }
+ }
+ else */
+ {
+ base = legitimize_pic_address (XEXP (addr, 0), mode, reg);
+ pic_ref = legitimize_pic_address (XEXP (addr, 1),
+ mode, base == reg ? NULL_RTX : reg);
+
+ if (GET_CODE (pic_ref) == CONST_INT)
+ pic_ref = plus_constant (base, INTVAL (pic_ref));
+ else
+ {
+ if (GET_CODE (pic_ref) == PLUS && CONSTANT_P (XEXP (pic_ref, 1)))
+ {
+ base = gen_rtx_PLUS (Pmode, base, XEXP (pic_ref, 0));
+ pic_ref = XEXP (pic_ref, 1);
+ }
+ pic_ref = gen_rtx_PLUS (Pmode, base, pic_ref);
+ }
+ }
+ }
+ }
+ return pic_ref;
+}
+
+static HOST_WIDE_INT m68k_GOT_alias_set PARAMS ((void));
+static HOST_WIDE_INT
+m68k_GOT_alias_set ()
+{
+ static HOST_WIDE_INT set = -1;
+ if (set == -1)
+ set = new_alias_set ();
+ return set;
+}
+
+static void
+cfv4e_encode_section_info (tree decl, rtx rtl, int first)
+{
+ if (flag_pic && TARGET_CFV4E)
+ {
+ /*rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
+ ? TREE_CST_RTL (decl) : DECL_RTL (decl)); */
+
+ if (GET_CODE (rtl) == MEM)
+ {
+ SYMBOL_REF_FLAG (XEXP (rtl, 0))
+ = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
+ || ! TREE_PUBLIC (decl));
+ }
+ }
+
+}
+
+
+/* Return nonzero if register old_reg can be renamed to register new_reg. */
+int
+m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
+ unsigned int new_reg)
+{
+
+ /* Interrupt functions can only use registers that have already been
+ saved by the prologue, even if they would normally be
+ call-clobbered. */
+
+ if (m68k_interrupt_function_p(current_function_decl)
+ && !regs_ever_live[new_reg])
+ return 0;
+
+ return 1;
+}
[-- Attachment #7: m68k.h_patch --]
[-- Type: application/octet-stream, Size: 12840 bytes --]
--- ../gcc_cvs/gcc/gcc/config/m68k/m68k.h 2004-03-10 10:37:14.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/m68k.h 2004-11-03 18:31:48.000000000 +0530
@@ -92,6 +92,10 @@
builtin_define ("__mcf5400__"); \
builtin_define ("__mcf5407__"); \
} \
+ if (TARGET_CFV4E) \
+ { \
+ builtin_define ("__mcfv4e__"); \
+ } \
if (TARGET_CF_HWDIV) \
builtin_define ("__mcfhwdiv__"); \
if (flag_pic) \
@@ -226,12 +230,18 @@
#define MASK_ID_SHARED_LIBRARY (1<<18)
#define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY)
+/* Compile for CFV4E */
+
+#define MASK_CFV4E (1<<19)
+#define TARGET_CFV4E (target_flags & MASK_CFV4E)
+
+
/* Compile for a CPU32. A 68020 without bitfields is a good
heuristic for a CPU32. */
#define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
/* Is the target a ColdFire? */
-#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
+#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4|MASK_CFV4E)
#define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
/* Which bits can be set by specifying a ColdFire */
@@ -265,7 +275,7 @@
{ "noshort", - MASK_SHORT, \
N_("Consider type `int' to be 32 bits wide") }, \
{ "68881", MASK_68881, "" }, \
- { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
+ { "soft-float", - (MASK_CFV4E|MASK_68040_ONLY|MASK_68881), \
N_("Generate code with library calls for floating point") }, \
{ "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
N_("Generate code for a 68040, without any new instructions") }, \
@@ -305,6 +315,10 @@
|MASK_BITFIELD|MASK_68881), \
N_("Generate code for a 5407") }, \
{ "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
+ { "cfv4e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040 \
+ |MASK_68040_ONLY|MASK_68020|MASK_BITFIELD|MASK_68881),\
+ N_("Generate code for a ColdFire CFV4E") }, \
+ { "cfv4e", (MASK_CFV4|MASK_CF_HWDIV|MASK_CFV4E), "" }, \
{ "68851", 0, \
N_("Generate code for a 68851") }, \
{ "no-68851", 0, \
@@ -386,7 +400,7 @@
/* target machine storage layout */
/* Define for XFmode extended real floating point support. */
-#define LONG_DOUBLE_TYPE_SIZE 96
+#define LONG_DOUBLE_TYPE_SIZE 96 /*(TARGET_CFV4E ? 64 : 96) */
/* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
instructions, we get proper intermediate rounding, otherwise we
@@ -524,7 +538,7 @@
{ \
int i; \
HARD_REG_SET x; \
- if (! TARGET_68881) \
+ if (! (TARGET_68881|TARGET_CFV4E)) \
{ \
COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
@@ -548,6 +562,13 @@
((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+/* A C expression that is nonzero if hard register NEW_REG can be
+ considered for use as a rename register for OLD_REG register. */
+
+#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
+ m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
+
+
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On the 68000, the cpu registers can hold any mode but the 68881 registers
can hold only SFmode or DFmode. */
@@ -558,7 +579,8 @@
|| ((REGNO) >= 16 && (REGNO) < 24 \
&& (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
- && GET_MODE_UNIT_SIZE (MODE) <= 12))
+ && GET_MODE_UNIT_SIZE (MODE) <= 12) \
+ && !(MODE == XFmode && TARGET_CFV4E))
/* Value is 1 if it is a good idea to tie two pseudo registers
@@ -566,7 +588,7 @@
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
- (! TARGET_68881 \
+ (! (TARGET_68881|TARGET_CFV4E) \
|| ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
== (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
@@ -682,7 +704,7 @@
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'a' ? ADDR_REGS : \
((C) == 'd' ? DATA_REGS : \
- ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
+ ((C) == 'f' ? ((TARGET_68881|TARGET_CFV4E) ? FP_REGS : \
NO_REGS) : \
NO_REGS)))
@@ -775,7 +797,7 @@
? DATA_REGS \
: (GET_CODE (X) == CONST_DOUBLE \
&& GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
- ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
+ ? ((TARGET_68881|TARGET_CFV4E) && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
? FP_REGS : NO_REGS) \
: (TARGET_PCREL \
&& (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
@@ -1151,11 +1173,11 @@
#else
#define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
#endif
-
#define LEGITIMATE_PIC_OPERAND_P(X) \
- (! symbolic_operand (X, VOIDmode) \
- || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
- || PCREL_GENERAL_OPERAND_OK)
+ ( (TARGET_CFV4E? legitimate_pic_operand_p(X) :\
+ (! symbolic_operand (X, VOIDmode) \
+ || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
+ || PCREL_GENERAL_OPERAND_OK) ) )
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
@@ -1222,9 +1244,9 @@
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& (TARGET_68020 \
|| ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
- || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
+ ||(!TARGET_CFV4E) && (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
&& flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
- || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
+ ||(!TARGET_CFV4E) && (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
&& flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
@@ -1276,16 +1298,29 @@
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& (INTVAL (XEXP (X, 1)) == 2 \
|| INTVAL (XEXP (X, 1)) == 4 \
- || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
+ || (INTVAL (XEXP (X, 1)) == 8 && (!TARGET_COLDFIRE|TARGET_CFV4E)))))
+
+/* If Coldfire and float, only accept addressing modes 2-5 */
+#define GO_IF_CFV4E_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
+{ if (LEGITIMATE_BASE_REG_P(X) \
+ || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
+ && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
+ || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
+ && (GET_CODE (XEXP (X, 1)) == CONST_INT) \
+ && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \
+ goto ADDR;}
/* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
+{ if (TARGET_CFV4E && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
+ { GO_IF_CFV4E_LEGITIMATE_ADDRESS(MODE, X, ADDR); \
+ } else { \
+ GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
GO_IF_INDEXED_ADDRESS (X, ADDR); \
if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
&& LEGITIMATE_INDEX_P (XEXP (X, 0)) \
&& GET_CODE (XEXP (X, 1)) == LABEL_REF) \
- goto ADDR; }
+ goto ADDR; }}
/* Don't call memory_address_noforce for the address to fetch
the switch offset. This address is ok as it stands (see above),
@@ -1321,7 +1356,9 @@
{ COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
if (ch && GET_CODE (XEXP (X, 1)) == REG \
&& GET_CODE (XEXP (X, 0)) == REG) \
- goto WIN; \
+ { if (TARGET_CFV4E && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
+ { COPY_ONCE (X); X = force_operand(X, 0); goto WIN;} \
+ else goto WIN; } \
if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
if (GET_CODE (XEXP (X, 0)) == REG \
|| (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
@@ -1332,7 +1369,10 @@
emit_move_insn (temp, val); \
COPY_ONCE (X); \
XEXP (X, 1) = temp; \
- goto WIN; } \
+ if (TARGET_CFV4E && GET_MODE_CLASS (MODE) == MODE_FLOAT \
+ && GET_CODE (XEXP (X, 0)) == REG) \
+ X = force_operand(X, 0); \
+ goto WIN; } \
else if (GET_CODE (XEXP (X, 1)) == REG \
|| (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
&& GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
@@ -1342,6 +1382,9 @@
emit_move_insn (temp, val); \
COPY_ONCE (X); \
XEXP (X, 0) = temp; \
+ if (TARGET_CFV4E && GET_MODE_CLASS (MODE) == MODE_FLOAT \
+ && GET_CODE (XEXP (X, 1)) == REG) \
+ X = force_operand(X, 0); \
goto WIN; }}}
/* Go to LABEL if ADDR (a legitimate address expression)
@@ -1706,7 +1749,49 @@
{"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
GT, LT, GE, LE}}, \
{"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},
-\f
+
+/* Additions for PIC for cfv4e */
+#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
+ do \
+ if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
+ { \
+ switch (XINT ((X), 1)) \
+ { \
+ case UNSPEC_PIC: \
+ /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
+ output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
+ fputs ("@GOT", (STREAM)); \
+ break; \
+ case UNSPEC_GOT: \
+ output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
+ fputs ("@GOT", (STREAM)); \
+ break; \
+ case UNSPEC_GOTOFF: \
+ output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
+ fputs ("@GOTOFF", (STREAM)); \
+ break; \
+ case UNSPEC_PLT: \
+ output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
+ fputs ("@PLT", (STREAM)); \
+ break; \
+ case UNSPEC_GOTPLT: \
+ output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
+ fputs ("@GOTPLT", (STREAM)); \
+ break; \
+ default: \
+ goto FAIL; \
+ } \
+ break; \
+ } \
+ else \
+ goto FAIL; \
+ while (0)
+
+#define SYMBOLIC_CONST(X) \
+ (GET_CODE (X) == SYMBOL_REF \
+ || GET_CODE (X) == LABEL_REF \
+ || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
+
/*
Local variables:
version-control: t
[-- Attachment #8: m68k.md_patch --]
[-- Type: application/octet-stream, Size: 41103 bytes --]
--- ../gcc_cvs/gcc/gcc/config/m68k/m68k.md 2004-01-31 11:48:27.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/m68k.md 2004-10-26 11:32:22.000000000 +0530
@@ -114,8 +114,13 @@
;; UNSPEC usage:
(define_constants
- [(UNSPEC_SIN 1)
- (UNSPEC_COS 2)
+ [(UNSPEC_SIN 1)
+ (UNSPEC_COS 2)
+ (UNSPEC_PIC 3)
+ (UNSPEC_GOT 4)
+ (UNSPEC_GOTOFF 5)
+ (UNSPEC_PLT 6)
+ (UNSPEC_GOTPLT 7)
])
;; UNSPEC_VOLATILE usage:
@@ -237,7 +242,7 @@
(define_expand "tstsf"
[(set (cc0)
(match_operand:SF 0 "general_operand" ""))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"
{
m68k_last_compare_had_fp_operands = 1;
@@ -246,18 +251,29 @@
(define_insn ""
[(set (cc0)
(match_operand:SF 0 "general_operand" "fdm"))]
- "TARGET_68881"
-{
+ "TARGET_68881 && !TARGET_CFV4E"
+ {
cc_status.flags = CC_IN_68881;
if (FP_REG_P (operands[0]))
return "ftst%.x %0";
return "ftst%.s %0";
})
+(define_insn "tstsf_v4e"
+ [(set (cc0)
+ (match_operand:SF 0 "general_operand" "fd<Q>U"))]
+ "TARGET_CFV4E"
+{
+ cc_status.flags = CC_IN_68881;
+ if (FP_REG_P (operands[0]))
+ return "ftst%.d %0";
+ return "ftst%.s %0";
+})
+
(define_expand "tstdf"
[(set (cc0)
(match_operand:DF 0 "general_operand" ""))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"
{
m68k_last_compare_had_fp_operands = 1;
@@ -266,14 +282,23 @@
(define_insn ""
[(set (cc0)
(match_operand:DF 0 "general_operand" "fm"))]
- "TARGET_68881"
+ "TARGET_68881 && !TARGET_CFV4E"
{
cc_status.flags = CC_IN_68881;
if (FP_REG_P (operands[0]))
return "ftst%.x %0";
return "ftst%.d %0";
})
-\f
+(define_insn "tstdf_v4e"
+ [(set (cc0)
+ (match_operand:DF 0 "general_operand" "f<Q>U"))]
+ "TARGET_CFV4E"
+{
+ cc_status.flags = CC_IN_68881;
+ return "ftst%.d %0";
+})
+
+
;; compare instructions.
(define_expand "cmpdi"
@@ -364,8 +389,8 @@
(define_insn ""
[(set (cc0)
- (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
- (match_operand:SI 1 "general_operand" "r,mrKs")))]
+ (compare (match_operand:SI 0 "nonimmediate_operand" "mrKi,r")
+ (match_operand:SI 1 "general_operand" "r,mrKi")))]
"TARGET_COLDFIRE"
{
if (REG_P (operands[1])
@@ -458,10 +483,12 @@
[(set (cc0)
(compare (match_operand:DF 0 "general_operand" "")
(match_operand:DF 1 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"
{
m68k_last_compare_had_fp_operands = 1;
+ if ( TARGET_CFV4E && (!reload_completed) )
+ operands[1] = force_reg(DFmode, operands[1]);
}")
(define_insn ""
@@ -494,14 +521,47 @@
#endif
})
+
+(define_insn "cmpdf_v4e"
+ [(set (cc0)
+ (compare (match_operand:DF 0 "general_operand" "f,<Q>U")
+ (match_operand:DF 1 "fpu_operand" "f<Q>U,f")))]
+ "TARGET_CFV4E"
+{
+ cc_status.flags = CC_IN_68881;
+#ifdef SGS_CMP_ORDER
+ if (FP_REG_P (operands[0]))
+ {
+ if (FP_REG_P (operands[1]))
+ return "fcmp%.d %0,%1";
+ else
+ return "fcmp%.d %0,%1";
+ }
+ cc_status.flags |= CC_REVERSED;
+ return "fcmp%.d %1,%0";
+#else
+ if (FP_REG_P (operands[0]))
+ {
+ if (FP_REG_P (operands[1]))
+ return "fcmp%.d %1,%0";
+ else
+ return "fcmp%.d %1,%0";
+ }
+ cc_status.flags |= CC_REVERSED;
+ return "fcmp%.d %0,%1";
+#endif
+})
+
(define_expand "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "")
(match_operand:SF 1 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881||TARGET_CFV4E"
"
{
m68k_last_compare_had_fp_operands = 1;
+ if ( TARGET_CFV4E && (!reload_completed) )
+ operands[1] = force_reg(SFmode, operands[1]);
}")
(define_insn ""
@@ -533,7 +593,37 @@
return "fcmp%.s %f0,%1";
#endif
})
-\f
+
+(define_insn "cmpsf_v4e"
+ [(set (cc0)
+ (compare (match_operand:SF 0 "general_operand" "f,<Q>U")
+ (match_operand:SF 1 "fpu_operand" "f<Q>U,f")))]
+ "TARGET_CFV4E"
+{
+ cc_status.flags = CC_IN_68881;
+#ifdef SGS_CMP_ORDER
+ if (FP_REG_P (operands[0]))
+ {
+ if (FP_REG_P (operands[1]))
+ return "fcmp%.d %0,%1";
+ else
+ return "fcmp%.s %0,%f1";
+ }
+ cc_status.flags |= CC_REVERSED;
+ return "fcmp%.s %1,%f0";
+#else
+ if (FP_REG_P (operands[0]))
+ {
+ if (FP_REG_P (operands[1]))
+ return "fcmp%.d %1,%0";
+ else
+ return "fcmp%.s %f1,%0";
+ }
+ cc_status.flags |= CC_REVERSED;
+ return "fcmp%.s %f0,%1";
+#endif
+})
+
;; Recognizers for btst instructions.
;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
@@ -721,13 +811,24 @@
""
"
{
- if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
+
+ if ( flag_pic && !TARGET_PCREL && TARGET_CFV4E )
+ {
+ m68k_expand_move (SImode, operands); DONE;
+
+ //rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
+ //operands[1] = legitimize_pic_address (operands[1], SImode, temp);
+ //emit_insn( gen_movsi_cfv4e_got(operands[0], operands[1], temp));
+ //DONE;
+ }
+ else if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
{
/* The source is an address which requires PIC relocation.
Call legitimize_pic_address with the source, mode, and a relocation
register (a new pseudo, or the final destination if reload_in_progress
is set). Then fall through normally */
rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
+
operands[1] = legitimize_pic_address (operands[1], SImode, temp);
}
else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
@@ -761,7 +862,19 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
(match_operand:SI 1 "general_operand" "g,r<Q>"))]
"TARGET_COLDFIRE"
- "* return output_move_simode (operands);")
+{
+ return output_move_simode (operands);
+})
+
+
+(define_insn "movsi_cfv4e_got"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
+ (match_operand:SI 1 "general_src_operand" "g"))]
+ "flag_pic && TARGET_CFV4E"
+{
+ return output_move_simode (operands);
+})
+
;; Special case of fullword move, where we need to get a non-GOT PIC
;; reference into an address register.
@@ -770,9 +883,9 @@
(match_operand:SI 1 "pcrel_address" ""))]
"TARGET_PCREL"
{
- if (push_operand (operands[0], SImode))
- return "pea %a1";
- return "lea %a1,%0";
+ if (push_operand (operands[0], SImode))
+ return "pea %a1";
+ return "lea %a1,%0";
})
(define_expand "movhi"
@@ -854,6 +967,36 @@
"!TARGET_COLDFIRE"
"")
+(define_expand "reload_insf"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (match_operand:SF 1 "general_operand" "mf"))
+ (clobber (match_operand:SI 2 "register_operand" "=&a"))]
+ "TARGET_CFV4E"
+ "
+{
+ if (emit_move_sequence (operands, SFmode, operands[2]))
+ DONE;
+
+ /* We don't want the clobber emitted, so handle this ourselves. */
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
+ DONE;
+}")
+
+(define_expand "reload_outsf"
+ [(set (match_operand:SF 0 "general_operand" "")
+ (match_operand:SF 1 "register_operand" "f"))
+ (clobber (match_operand:SI 2 "register_operand" "=&a"))]
+ "TARGET_CFV4E"
+ "
+{
+ if (emit_move_sequence (operands, SFmode, operands[2]))
+ DONE;
+
+ /* We don't want the clobber emitted, so handle this ourselves. */
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
+ DONE;
+}")
+
(define_expand "movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "general_operand" ""))]
@@ -912,19 +1055,192 @@
return "move%.l %1,%0";
})
-(define_insn ""
+;(define_insn ""
+; [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
+; (match_operand:SF 1 "general_operand" "g,r"))]
+; "TARGET_COLDFIRE"
+;{
+; return "move%.l %1,%0";
+;})
+
+(define_insn "movsf_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f,m")
+ (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m,f"))]
+ "TARGET_CFV4E"
+{
+ if (which_alternative == 4 || which_alternative == 5) {
+ rtx xoperands[2];
+ REAL_VALUE_TYPE r;
+ long l;
+ REAL_VALUE_FROM_CONST_DOUBLE(r, operands[1]);
+ REAL_VALUE_TO_TARGET_SINGLE(r, l);
+ xoperands[0] = operands[0];
+ xoperands[1] = GEN_INT(l);
+ if (which_alternative == 5) {
+ if (l == 0) {
+ if (ADDRESS_REG_P (xoperands[0]))
+ output_asm_insn("sub%.l %0,%0", xoperands);
+ else
+ output_asm_insn("clr%.l %0", xoperands);
+ } else
+ if (GET_CODE (operands[0]) == MEM
+ && symbolic_operand (XEXP (operands[0], 0), SImode))
+ output_asm_insn("move%.l %1,%-;move%.l %+,%0", xoperands);
+ else
+ output_asm_insn("move%.l %1,%0", xoperands);
+ return "\";
+ }
+ if (l != 0)
+ output_asm_insn("move%.l %1,%-;fsmove%.s %+,%0", xoperands);
+ else
+ output_asm_insn("clr%.l %-;fsmove%.s %+,%0", xoperands);
+ return "\";
+ }
+ if (FP_REG_P (operands[0]))
+ {
+ if (ADDRESS_REG_P (operands[1]))
+ return "move%.l %1,%-;f%$smove%.s %+,%0";
+ if (FP_REG_P (operands[1]))
+ return "f%$move%.d %1,%0";
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ return output_move_const_single (operands);
+ return "f%$move%.s %f1,%0";
+ }
+ if (FP_REG_P (operands[1]))
+ {
+ if (ADDRESS_REG_P (operands[0]))
+ return "fmove%.s %1,%-;move%.l %+,%0";
+ return "fmove%.s %f1,%0";
+ }
+ if (operands[1] == CONST0_RTX (SFmode)
+ /* clr insns on 68000 read before writing.
+ This isn't so on the 68010, but we have no TARGET_68010. */
+ && ((TARGET_68020 || TARGET_COLDFIRE)
+ || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+ {
+ if (ADDRESS_REG_P (operands[0]))
+ {
+ /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
+ if (!TARGET_68040 && !TARGET_68060)
+ return "sub%.l %0,%0";
+ else
+ {
+#ifdef MOTOROLA
+#ifdef SGS
+ /* Many SGS assemblers croak on size specifiers for constants. */
+ return "lea 0,%0";
+#else
+ return "lea 0.w,%0";
+#endif
+#else
+ return "lea 0:w,%0";
+#endif
+ }
+ }
+ /* moveq is faster on the 68000. */
+ if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
+ {
+#if defined(MOTOROLA) && !defined(CRDS)
+ return "moveq%.l %#0,%0";
+#else
+ return "moveq %#0,%0";
+#endif
+ }
+ return "clr%.l %0";
+ }
+ return "move%.l %1,%0";
+})
+
+(define_insn "movsf_cf"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
- (match_operand:SF 1 "general_operand" "g,r"))]
- "TARGET_COLDFIRE"
+ (match_operand:SF 1 "general_operand" "g,r"))]
+ "TARGET_COLDFIRE && !TARGET_CFV4E"
{
- return "move%.l %1,%0";
+ return "move%.l %1,%0";})
+
+(define_expand "reload_indf"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (match_operand:DF 1 "general_operand" "mf"))
+ (clobber (match_operand:SI 2 "register_operand" "=&a"))]
+ "TARGET_CFV4E"
+ {
+ if (emit_move_sequence (operands, DFmode, operands[2]))
+ DONE;
+
+ /* We don't want the clobber emitted, so handle this ourselves. */
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
+ DONE;
})
+(define_expand "reload_outdf"
+ [(set (match_operand:DF 0 "general_operand" "")
+ (match_operand:DF 1 "register_operand" "f"))
+ (clobber (match_operand:SI 2 "register_operand" "=&a"))]
+ "TARGET_CFV4E"
+{
+ if (emit_move_sequence (operands, DFmode, operands[2]))
+ DONE;
+
+ /* We don't want the clobber emitted, so handle this ourselves. */
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
+ DONE;
+})
+
+(define_insn ""
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g,f")
+ (match_operand:SF 1 "general_operand" "g,r,f"))]
+ "TARGET_COLDFIRE"
+{
+ return \"move%.l %1,%0\";})
+
(define_expand "movdf"
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(match_operand:DF 1 "general_operand" ""))]
""
- "")
+{
+ if (TARGET_CFV4E)
+ if (emit_move_sequence (operands, DFmode, 0))
+ DONE;
+})
+
+; [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r")
+; (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r"))]
+
+(define_insn "movdf_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,f,m,f")
+ (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,f,E"))]
+ "TARGET_CFV4E"
+{
+ if (which_alternative == 4)
+ return "move%.l %1,%0;move%.l %R1,%R0";
+ if (which_alternative == 2)
+ return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0";
+ if (which_alternative == 3)
+ return "move%.l %R1,%-;move%.l %1,%-;f%&move%.d %+,%0";
+ if (which_alternative == 7) {
+ rtx xoperands[3];
+ REAL_VALUE_TYPE r;
+ long l[2];
+ REAL_VALUE_FROM_CONST_DOUBLE(r, operands[1]);
+ REAL_VALUE_TO_TARGET_DOUBLE(r, l);
+ xoperands[0] = operands[0];
+ xoperands[1] = GEN_INT(l[0]);
+ xoperands[2] = GEN_INT(l[1]);
+ if (operands[1] == CONST0_RTX (DFmode))
+ output_asm_insn("clr%.l %-;clr%.l %-;fdmove%.d %+,%0",
+ xoperands);
+ else
+ if (l[1] == 0)
+ output_asm_insn("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0",
+ xoperands);
+ else
+ output_asm_insn("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0",
+ xoperands);
+ return "\";
+ }
+ return "fmove%.d %1,%0";
+})
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
@@ -1542,16 +1858,37 @@
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
"TARGET_68020 || TARGET_COLDFIRE"
"extb%.l %0")
-\f
+
;; Conversions between float and double.
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(float_extend:DF
(match_operand:SF 1 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "extendsfdf2_v4e"
+ [(set (match_operand:DF 0 "general_operand" "=f,f")
+ (float_extend:DF
+ (match_operand:SF 1 "general_operand" "f,<Q>U")))]
+ "TARGET_CFV4E"
+{
+ if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
+ {
+ if (REGNO (operands[0]) == REGNO (operands[1]))
+ {
+ /* Extending float to double in an fp-reg is a no-op.
+ NOTICE_UPDATE_CC has already assumed that the
+ cc will be set. So cancel what it did. */
+ cc_status = cc_prev_status;
+ return "\";
+ }
+ return "f%&move%.d %1,%0";
+ }
+ return "f%&move%.s %f1,%0";
+})
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
(float_extend:DF
@@ -1570,8 +1907,6 @@
}
return "f%&move%.x %1,%0";
}
- if (FP_REG_P (operands[0]))
- return "f%&move%.s %f1,%0";
if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
{
output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
@@ -1587,9 +1922,18 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(float_truncate:SF
(match_operand:DF 1 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "truncdfsf2_v4e"
+ [(set (match_operand:SF 0 "general_operand" "=f,d<Q>U")
+ (float_truncate:SF
+ (match_operand:DF 1 "general_operand" "<Q>U,f")))]
+ "TARGET_CFV4E"
+ "@
+ f%$move%.d %1,%0
+ fmove%.s %1,%0")
+
;; On the '040 we can truncate in a register accurately and easily.
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
@@ -1620,9 +1964,16 @@
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(float:SF (match_operand:SI 1 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "floatsisf2_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (float:SF (match_operand:SI 1 "general_operand" "d<Q>U")))]
+ "TARGET_CFV4E"
+ "f%$move%.l %1,%0")
+
+
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(float:SF (match_operand:SI 1 "general_operand" "dmi")))]
@@ -1632,36 +1983,90 @@
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(float:DF (match_operand:SI 1 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "floatsidf2_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (float:DF (match_operand:SI 1 "general_operand" "d<Q>U")))]
+ "TARGET_CFV4E"
+ "f%&move.l %1,%0")
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(float:DF (match_operand:SI 1 "general_operand" "dmi")))]
"TARGET_68881"
"f%&move%.l %1,%0")
-(define_insn "floathisf2"
+(define_expand "floathisf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(float:SF (match_operand:HI 1 "general_operand" "dmn")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "floathisf2_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (float:SF (match_operand:HI 1 "general_operand" "d<Q>U")))]
+ "TARGET_CFV4E"
+ "fsmove%.w %1,%0")
+
+(define_insn "floathisf2_68881"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
"TARGET_68881"
"f%$move%.w %1,%0")
-(define_insn "floathidf2"
+(define_expand "floathidf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(float:DF (match_operand:HI 1 "general_operand" "dmn")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "floathidf2_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (float:DF (match_operand:HI 1 "general_operand" "d<Q>U")))]
+ "TARGET_CFV4E"
+ "fmove%.w %1,%0")
+
+(define_insn "floathidf2_68881"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
"TARGET_68881"
"fmove%.w %1,%0")
-(define_insn "floatqisf2"
+(define_expand "floatqisf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(float:SF (match_operand:QI 1 "general_operand" "dmn")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "floatqisf2_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (float:SF (match_operand:QI 1 "general_operand" "d<Q>U")))]
+ "TARGET_CFV4E"
+ "fsmove%.b %1,%0")
+
+(define_insn "floatqisf2_68881"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
"TARGET_68881"
"fmove%.b %1,%0")
-(define_insn "floatqidf2"
+(define_expand "floatqidf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(float:DF (match_operand:QI 1 "general_operand" "dmn")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "floatqidf2_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (float:DF (match_operand:QI 1 "general_operand" "d<Q>U")))]
+ "TARGET_CFV4E"
+ "fmove%.b %1,%0")
+
+(define_insn "floatqidf2_68881"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
"TARGET_68881"
"f%&move%.b %1,%0")
@@ -1706,9 +2111,23 @@
;; Convert a float to a float whose value is an integer.
;; This is the first stage of converting it to an integer type.
-(define_insn "ftruncdf2"
+(define_expand "ftruncdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
+ "(TARGET_68881 && !TARGET_68040) || TARGET_CFV4E"
+ "")
+
+(define_insn "ftruncdf2_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (fix:DF (match_operand:DF 1 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+{
+ return "fintrz%.d %1,%0";
+})
+
+(define_insn "ftruncdf2_68881"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
"TARGET_68881 && !TARGET_68040"
{
if (FP_REG_P (operands[1]))
@@ -1716,9 +2135,25 @@
return "fintrz%.d %f1,%0";
})
-(define_insn "ftruncsf2"
+(define_expand "ftruncsf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
+ "(TARGET_68881 && !TARGET_68040) || TARGET_CFV4E"
+ "")
+
+(define_insn "ftruncsf2_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (fix:SF (match_operand:SF 1 "general_operand" "d<Q>U")))]
+ "TARGET_CFV4E"
+{
+ if (FP_REG_P (operands[1]))
+ return "fintrz%.d %1,%0";
+ return "fintrz%.s %1,%0";
+})
+
+(define_insn "ftruncsf2_68881"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
"TARGET_68881 && !TARGET_68040"
{
if (FP_REG_P (operands[1]))
@@ -1728,42 +2163,114 @@
;; Convert a float whose value is an integer
;; to an actual integer. Second stage of converting float to integer type.
-(define_insn "fixsfqi2"
+(define_expand "fixsfqi2"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(fix:QI (match_operand:SF 1 "general_operand" "f")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "fixsfqi2_v4e"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
+ (fix:QI (match_operand:SF 1 "general_operand" "f")))]
+ "TARGET_CFV4E"
+ "fmove%.b %1,%0")
+
+(define_insn "fixsfqi2_68881"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
+ (fix:QI (match_operand:SF 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.b %1,%0")
-(define_insn "fixsfhi2"
+(define_expand "fixsfhi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(fix:HI (match_operand:SF 1 "general_operand" "f")))]
+ "TARGET_68881|| TARGET_CFV4E"
+ "")
+
+(define_insn "fixsfhi2_v4e"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
+ (fix:HI (match_operand:SF 1 "general_operand" "f")))]
+ "TARGET_CFV4E"
+ "fmove%.w %1,%0")
+
+(define_insn "fixsfhi2_68881"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
+ (fix:HI (match_operand:SF 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.w %1,%0")
-(define_insn "fixsfsi2"
+(define_expand "fixsfsi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(fix:SI (match_operand:SF 1 "general_operand" "f")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "fixsfsi2_v4e"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
+ (fix:SI (match_operand:SF 1 "general_operand" "f")))]
+ "TARGET_CFV4E"
+ "fmove%.l %1,%0")
+
+(define_insn "fixsfsi2_68881"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
+ (fix:SI (match_operand:SF 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.l %1,%0")
-(define_insn "fixdfqi2"
+(define_expand "fixdfqi2"
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(fix:QI (match_operand:DF 1 "general_operand" "f")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "fixdfqi2_v4e"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
+ (fix:QI (match_operand:DF 1 "general_operand" "f")))]
+ "TARGET_CFV4E"
+ "fmove%.b %1,%0")
+
+(define_insn "fixdfqi2_68881"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
+ (fix:QI (match_operand:DF 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.b %1,%0")
-(define_insn "fixdfhi2"
+(define_expand "fixdfhi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(fix:HI (match_operand:DF 1 "general_operand" "f")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "fixdfhi2_v4e"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
+ (fix:HI (match_operand:DF 1 "general_operand" "f")))]
+ "TARGET_CFV4E"
+ "fmove%.w %1,%0")
+
+(define_insn "fixdfhi2_68881"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
+ (fix:HI (match_operand:DF 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.w %1,%0")
-(define_insn "fixdfsi2"
+(define_expand "fixdfsi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(fix:SI (match_operand:DF 1 "general_operand" "f")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "fixdfsi2_v4e"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
+ (fix:SI (match_operand:DF 1 "general_operand" "f")))]
+ "TARGET_CFV4E"
+ "fmove%.l %1,%0")
+
+(define_insn "fixdfsi2_68881"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
+ (fix:SI (match_operand:DF 1 "general_operand" "f")))]
"TARGET_68881"
"fmove%.l %1,%0")
-\f
+
;; add instructions
(define_insn "adddi_lshrdi_63"
@@ -2219,9 +2726,17 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(plus:DF (match_operand:DF 1 "general_operand" "")
(match_operand:DF 2 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "adddf3_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (plus:DF (match_operand:DF 1 "general_operand" "%0")
+ (match_operand:DF 2 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+ "fadd%.d %2,%0")
+
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
@@ -2258,8 +2773,20 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(plus:SF (match_operand:SF 1 "general_operand" "")
(match_operand:SF 2 "general_operand" "")))]
- "TARGET_68881"
- "")
+ "(TARGET_68881 || TARGET_CFV4E)"
+ "
+ ")
+
+(define_insn "addsf3_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (plus:SF (match_operand:SF 1 "general_operand" "%0")
+ (match_operand:SF 2 "general_operand" "fd<Q>U")))]
+ "TARGET_CFV4E"
+{
+ if (FP_REG_P (operands[2]))
+ return "f%$add%.d %2,%0";
+ return "fadd%.s %2,%0";
+})
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
@@ -2457,9 +2984,16 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(minus:DF (match_operand:DF 1 "general_operand" "")
(match_operand:DF 2 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "subdf3_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (minus:DF (match_operand:DF 1 "general_operand" "0")
+ (match_operand:DF 2 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+ "fsub%.d %2,%0")
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(minus:DF (match_operand:DF 1 "general_operand" "0")
@@ -2496,9 +3030,21 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(minus:SF (match_operand:SF 1 "general_operand" "")
(match_operand:SF 2 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "subsf3_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (minus:SF (match_operand:SF 1 "general_operand" "0")
+ (match_operand:SF 2 "general_operand" "f<Q>Ud")))]
+ "TARGET_CFV4E"
+{
+ if (!FP_REG_P (operands[2]))
+ return "fsub%.s %2,%0";
+ return "fssub%.d %2,%0";
+})
+
+
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(minus:SF (match_operand:SF 1 "general_operand" "0")
@@ -2778,9 +3324,16 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(mult:DF (match_operand:DF 1 "general_operand" "")
(match_operand:DF 2 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "muldf3_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (mult:DF (match_operand:DF 1 "general_operand" "%0")
+ (match_operand:DF 2 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+ "fmul%.d %2,%0")
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
@@ -2824,8 +3377,18 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(mult:SF (match_operand:SF 1 "general_operand" "")
(match_operand:SF 2 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "mulsf3_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (mult:SF (match_operand:SF 1 "general_operand" "%0")
+ (match_operand:SF 2 "general_operand" "f<Q>Ud")))]
+ "TARGET_CFV4E"
+{
+ if (!FP_REG_P (operands[2]))
+ return "fmul%.s %2,%0";
+ return "fsmul%.d %2,%0";
+})
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
@@ -2881,9 +3444,16 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(div:DF (match_operand:DF 1 "general_operand" "")
(match_operand:DF 2 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "divdf3_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (div:DF (match_operand:DF 1 "general_operand" "0")
+ (match_operand:DF 2 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+ "fdiv%.d %2,%0")
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(div:DF (match_operand:DF 1 "general_operand" "0")
@@ -2920,9 +3490,20 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(div:SF (match_operand:SF 1 "general_operand" "")
(match_operand:SF 2 "general_operand" "")))]
- "TARGET_68881"
+ "TARGET_68881 || TARGET_CFV4E"
"")
+(define_insn "divsf3_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (div:SF (match_operand:SF 1 "general_operand" "0")
+ (match_operand:SF 2 "general_operand" "f<Q>Ud")))]
+ "TARGET_CFV4E"
+{
+ if (FP_REG_P (operands[2]))
+ return "fsdiv%.d %2,%0";
+ return "fdiv%.s %2,%0";
+})
+
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(div:SF (match_operand:SF 1 "general_operand" "0")
@@ -3669,9 +4250,8 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(neg:SF (match_operand:SF 1 "general_operand" "")))]
""
- "
{
- if (!TARGET_68881)
+ if (!TARGET_68881 && !TARGET_CFV4E)
{
rtx result;
rtx target;
@@ -3690,7 +4270,14 @@
emit_move_insn (operands[0], operands[0]);
DONE;
}
-}")
+})
+
+
+(define_insn "negsf2_v4e"
+ [(set (match_operand:SF 0 "general_operand" "=f")
+ (neg:SF (match_operand:SF 1 "general_operand" "d<Q>U")))]
+ "TARGET_CFV4E"
+ "f%$neg%.s %1,%0")
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
@@ -3707,13 +4294,28 @@
return "f%$neg%.s %f1,%0";
})
+(define_insn ""
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
+ (neg:SF (match_operand:SF 1 "general_operand" "fd<Q>U,0")))]
+ "TARGET_CFV4E"
+{
+ if (DATA_REG_P (operands[0]))
+ {
+ operands[1] = GEN_INT (31);
+ return "bchg %1,%0";
+ }
+ if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
+ return "fsneg%.d %1,%0";
+ return "fsneg%.s %1,%0";
+})
+
(define_expand "negdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(neg:DF (match_operand:DF 1 "general_operand" "")))]
""
"
{
- if (!TARGET_68881)
+ if (!TARGET_68881 && !TARGET_CFV4E)
{
rtx result;
rtx target;
@@ -3741,6 +4343,12 @@
}
}")
+(define_insn "negdf2_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (neg:DF (match_operand:DF 1 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+ "fneg%.d %1,%0")
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
(neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
@@ -3752,15 +4360,47 @@
return "bchg %1,%0";
}
if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
- return "f%&neg%.x %1,%0";
- return "f%&neg%.d %f1,%0";
+ return \"f%&neg%.x %1,%0\";
+ return \"f%&neg%.d %f1,%0\";
})
-\f
+
+(define_insn ""
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
+ (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
+ "TARGET_CFV4E"
+{
+ if (DATA_REG_P (operands[0]))
+ {
+ operands[1] = GEN_INT (31);
+ return "bchg %1,%0";
+ }
+ if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
+ return "fdneg%.d %1,%0";
+ return "fdneg%.d %1,%0";
+})
+
;; Sqrt instruction for the 68881
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "sqrtsf2_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (sqrt:SF (match_operand:SF 1 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+{
+ if (FP_REG_P (operands[1]))
+ return "fssqrt%.d %1,%0";
+ else
+ return "fssqrt%.s %1,%0";
+})
+
+(define_insn "sqrtsf2_68881"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
"TARGET_68881"
{
if (FP_REG_P (operands[1]))
@@ -3772,6 +4412,20 @@
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
+ "TARGET_68881 || TARGET_CFV4E"
+ "")
+
+(define_insn "sqrtdf2_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (sqrt:DF (match_operand:DF 1 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+{
+ return "fdsqrt%.d %1,%0";
+})
+
+(define_insn "sqrtdf2_68881"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
"TARGET_68881"
{
if (FP_REG_P (operands[1]))
@@ -3789,7 +4443,7 @@
""
"
{
- if (!TARGET_68881)
+ if (!TARGET_68881 || !TARGET_CFV4E)
{
rtx result;
rtx target;
@@ -3810,6 +4464,16 @@
}
}")
+(define_insn "abssf_v4e"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
+ (abs:SF (match_operand:SF 1 "general_operand" "fd<Q>U")))]
+ "TARGET_CFV4E"
+{
+ if (FP_REG_P (operands[1]))
+ return "fsabs.d %1,%0";
+ return "fsabs%.s %1,%0";
+})
+
(define_insn ""
[(set (match_operand:SF 0 "nonimmediate_operand" "=f")
(abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
@@ -3826,7 +4490,7 @@
""
"
{
- if (!TARGET_68881)
+ if (!TARGET_68881 || TARGET_CFV4E)
{
rtx result;
rtx target;
@@ -3854,6 +4518,14 @@
}
}")
+(define_insn "absdf_v4e"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
+ (abs:DF (match_operand:DF 1 "general_operand" "f<Q>U")))]
+ "TARGET_CFV4E"
+{
+ return "fdabs%.d %1,%0";
+})
+
(define_insn ""
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
@@ -5087,7 +5759,7 @@
""
"
{
- if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+ if ((TARGET_68060 || TARGET_CFV4E ) && m68k_last_compare_had_fp_operands)
{
m68k_last_compare_had_fp_operands = 0;
FAIL;
@@ -5109,7 +5781,7 @@
""
"
{
- if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+ if ( (TARGET_68060 || TARGET_CFV4E) && m68k_last_compare_had_fp_operands)
{
m68k_last_compare_had_fp_operands = 0;
FAIL;
@@ -5131,7 +5803,7 @@
""
"
{
- if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+ if ((TARGET_68060||TARGET_CFV4E) && m68k_last_compare_had_fp_operands)
{
m68k_last_compare_had_fp_operands = 0;
FAIL;
@@ -5168,7 +5840,7 @@
""
"
{
- if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+ if ((TARGET_68060||TARGET_CFV4E) && m68k_last_compare_had_fp_operands)
{
m68k_last_compare_had_fp_operands = 0;
FAIL;
@@ -5205,7 +5877,7 @@
""
"
{
- if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+ if ((TARGET_68060 || TARGET_CFV4E)&& m68k_last_compare_had_fp_operands)
{
m68k_last_compare_had_fp_operands = 0;
FAIL;
@@ -5242,7 +5914,7 @@
""
"
{
- if (TARGET_68060 && m68k_last_compare_had_fp_operands)
+ if ((TARGET_68060|| TARGET_CFV4E) && m68k_last_compare_had_fp_operands)
{
m68k_last_compare_had_fp_operands = 0;
FAIL;
@@ -6408,6 +7080,18 @@
""
"
{
+rtx insn;
+ if (flag_pic && TARGET_CFV4E)
+ {
+ if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
+ && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
+ current_function_uses_pic_offset_table = 1;
+
+ //if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
+ XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
+ insn = emit_call_insn (gen_call_exp (operands[0], operands[1]));
+ DONE;
+ }
if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
}")
@@ -6439,6 +7123,24 @@
return "";
})
+
+/* Added for handling of PIC in cfv4e */
+(define_expand "call_exp"
+ [(call (match_operand:QI 0 "constant_call_address_operand" "")
+ (match_operand 1 "" ""))]
+ "flag_pic && TARGET_CFV4E"
+ "")
+
+/* Added for handling of PIC in cfv4e */
+(define_insn "*call_0"
+ [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
+ (match_operand 1 "" ""))]
+ "flag_pic && TARGET_CFV4E"
+ "*
+{
+ return \"jsr %a1@GOT(%%a5)\";
+}")
+
;; Call subroutine, returning value in operand 0
;; (which must be a hard register).
;; See comments before "call" regarding PIC calls.
@@ -6450,7 +7152,19 @@
""
"
{
- if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+rtx insn;
+ if ( flag_pic && TARGET_CFV4E )
+ {
+ if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
+ && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
+ current_function_uses_pic_offset_table = 1;
+ //if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
+ XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
+ insn = emit_call_insn (gen_call_value_exp (operands[0], operands[1],
+ operands[2]));
+ DONE;
+ }
+ else if ( flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
}")
@@ -6475,12 +7189,34 @@
(call (match_operand:QI 1 "memory_operand" "o")
(match_operand:SI 2 "general_operand" "g")))]
;; Operand 2 not really used on the m68000.
- "flag_pic"
+ "flag_pic "
{
m68k_output_pic_call(operands[1]);
return "";
})
+/* Added for handling of PIC in cfv4e */
+(define_expand "call_value_exp"
+ [(set (match_operand 0 "" "")
+ (call (match_operand:QI 1 "" "")
+ (match_operand:SI 2 "" "")))]
+ "flag_pic && TARGET_CFV4E"
+ "")
+
+/* Added for handling of PIC in cfv4e */
+(define_insn "*call_value_0"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
+ (match_operand:SI 2 "" "")))]
+ "flag_pic && TARGET_CFV4E"
+ "*
+{
+ return \"jsr %a1@GOT(%%a5)\";
+}")
+
+
+
+
;; Call subroutine returning any type.
(define_expand "untyped_call"
@@ -6839,6 +7575,8 @@
return "";
})
+
+
\f
(define_expand "tstxf"
[(set (cc0)
@@ -6849,7 +7587,7 @@
(define_insn ""
[(set (cc0)
(match_operand:XF 0 "nonimmediate_operand" "fm"))]
- "TARGET_68881"
+ "TARGET_68881 && !TARGET_CFV4E"
{
cc_status.flags = CC_IN_68881;
return "ftst%.x %0";
[-- Attachment #9: m68k-none.h_patch --]
[-- Type: application/octet-stream, Size: 1300 bytes --]
--- ../gcc_cvs/gcc/gcc/config/m68k/m68k-none.h 2003-10-11 08:36:45.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/m68k-none.h 2004-10-04 17:32:53.000000000 +0530
@@ -81,7 +81,7 @@
#undef ASM_SPEC
#define ASM_SPEC "\
-%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881} %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040} %{m68020-60:-mc68040} %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%(asm_cpu_default)}}}}}}}}}}}}}}}}}} \
+%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881} %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040} %{m68020-60:-mc68040} %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:%(asm_cpu_default)}}}}}}}}}}}}}}}}}}} \
%{fPIC:--pcrel} %{fpic:--pcrel} %{msep-data:--pcrel} %{mid-shared-library:--pcrel} \
"
[-- Attachment #10: m68k-protos.h_patch --]
[-- Type: application/octet-stream, Size: 1166 bytes --]
--- ../gcc_cvs/gcc/gcc/config/m68k/m68k-protos.h 2003-10-11 12:05:53.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/m68k-protos.h 2004-11-03 18:32:23.000000000 +0530
@@ -50,6 +50,7 @@
/* Functions from m68k.c used in macros. */
extern bool symbolic_operand (rtx, enum machine_mode);
+extern bool symbolic_operand_cfv4e (rtx, enum machine_mode);
extern int standard_68881_constant_p (rtx);
extern void print_operand_address (FILE *, rtx);
extern void print_operand (FILE *, rtx, int);
@@ -57,8 +58,12 @@
extern int general_src_operand (rtx, enum machine_mode);
extern int nonimmediate_src_operand (rtx, enum machine_mode);
extern int memory_src_operand (rtx, enum machine_mode);
+extern int fpu_operand PARAMS ((rtx, enum machine_mode));
+extern int general_no_elim_operand PARAMS ((rtx, enum machine_mode));
+extern int constant_call_address_operand PARAMS ((rtx, enum machine_mode));
extern int pcrel_address (rtx, enum machine_mode);
extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
+extern int m68k_hard_regno_rename_ok(unsigned int, unsigned int);
#endif /* RTX_CODE */
extern int flags_in_68881 (void);
[-- Attachment #11: t-m68k-elf_patch --]
[-- Type: application/octet-stream, Size: 1072 bytes --]
--- ../gcc_cvs/gcc/gcc/config/m68k/t-m68kelf 2003-08-21 06:33:37.000000000 +0530
+++ ../gcc-3.4.0/gcc/config/m68k/t-m68kelf 2004-10-04 17:32:58.000000000 +0530
@@ -12,14 +12,14 @@
echo '#define EXTFLOAT' > xfgnulib.c
cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
-MULTILIB_OPTIONS = m68000/m68020/m5200/m5206e/m528x/m5307/m5407/mcpu32/m68040/m68060 m68881/msoft-float
+MULTILIB_OPTIONS = mcfv4e/m68000/m68020/m5200/m5206e/m528x/m5307/m5407/mcpu32/m68040/m68060 m68881/msoft-float
MULTILIB_DIRNAMES =
MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m5206e=m5272
MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float \
m5206e/m68881 m5206e/msoft-float m528x/m68881 m528x/msoft-float \
m5307/m68881 m5307/msoft-float m5407/m68881 m5407/msoft-float \
mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float \
- m68060/m68881 m68060/msoft-float
+ m68060/m68881 m68060/msoft-float mcfv4e/m68881
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2004-12-19 0:14 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2004-12-13 7:20 New target for Coldfire v4e? C Jaiprakash, Noida
2004-12-13 13:27 ` Bernardo Innocenti
2004-12-13 14:30 ` Peter Barada
2004-12-13 18:13 ` Bernardo Innocenti
2004-12-13 18:43 ` Peter Barada
2004-12-14 1:08 ` Bernardo Innocenti
2004-12-14 2:24 ` Peter Barada
2004-12-14 2:34 ` Peter Barada
2004-12-14 8:26 ` Bernardo Innocenti
2004-12-14 14:24 ` Peter Barada
2004-12-14 18:34 ` Bernardo Innocenti
2004-12-14 20:14 ` Joel Sherrill <joel@OARcorp.com>
2004-12-14 20:57 ` Peter Barada
2004-12-14 21:41 ` Joel Sherrill <joel@OARcorp.com>
2004-12-14 22:12 ` Peter Barada
2004-12-17 14:10 ` Gunther Nikl
2004-12-17 14:30 ` Peter Barada
2004-12-19 0:14 ` Richard Henderson
2004-12-14 7:16 C Jaiprakash, Noida
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