From: Paul E Murphy <murphyp@linux.ibm.com>
To: Nicholas Piggin <npiggin@gmail.com>, linuxppc-dev@lists.ozlabs.org
Cc: gcc@gcc.gnu.org, libc-alpha@sourceware.org
Subject: Re: [RFC Linux patch] powerpc: add documentation for HWCAPs
Date: Mon, 23 May 2022 09:19:47 -0500 [thread overview]
Message-ID: <27e05114-fd3a-b7cc-1bdd-05d8eaf0b483@linux.ibm.com> (raw)
In-Reply-To: <1653091346.1a5h1ae3pd.astroid@bobo.none>
On 5/20/22 7:11 PM, Nicholas Piggin wrote:
> Excerpts from Paul E Murphy's message of May 21, 2022 12:21 am:
>>
>>
>> On 5/20/22 12:15 AM, Nicholas Piggin via Gcc wrote:
>>> +PPC_FEATURE2_TAR
>>> + VSX facility is available.
>>
>> Was manipulating the tar spr was once a privileged instruction, is this
>> a hint userspace can use the related instructions?
>
> It can be disabled with facility control, and I guess there was
> some consideration for how it might be used, e.g., "system software"
> could use it for its own purpose then clear the bit for the application.
>
> In practice I don't really know what makes use of this or whether
> anything sanely can, it's marked reserved in the ABI. Would be
> interesting to know whether there is much benefit to use it in the
> compiler. The kernel could actually use it for something nifty if we
> were able to prevent userspace from accessing it entirely...
It might be useful as a scratch register for indirect branches in some
odd cases, such as golang's preemptive userspace threading. Though, it
seems more trouble than its worth for a very limited benefit.
>
>>> +
>>> +PPC_FEATURE2_HAS_IEEE128
>>> + IEEE 128 is available? What instructions/data?
>>
>> Maybe something like "IEEE 128 binary floating point instructions are
>> supported. Individual instruction availability is dependent on the
>> reported architecture version."?
>
> Right, I just didn't know what architectural class of instructions
> those are. Is it just VSX in general or are there some specific
> things we can name?
I think ISA 3.1 buckets this into an OpenPOWER Linux Optional Feature
for "Quad-precision floating-point (QFP)". I guess ISA 3.0 predates
those categorizations.
>>> +PPC_FEATURE2_MMA
>>> + MMA facility is available.
>>
>> Maybe another note that specific instruction availability may depend on
>> the reported architecture version?
Yep. I wonder if it would help to note how these align (or don't) with
the various OpenPOWER features.
next prev parent reply other threads:[~2022-05-23 14:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-20 5:15 Nicholas Piggin
2022-05-20 9:21 ` Michael Ellerman
2022-05-20 12:06 ` Nicholas Piggin
2022-05-20 14:21 ` Paul E Murphy
2022-05-20 17:42 ` Segher Boessenkool
2022-05-21 0:11 ` Nicholas Piggin
2022-05-23 14:19 ` Paul E Murphy [this message]
2022-05-20 16:58 ` Peter Bergner
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