From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5864 invoked by alias); 6 May 2010 09:08:24 -0000 Received: (qmail 5828 invoked by uid 22791); 6 May 2010 09:08:23 -0000 X-SWARE-Spam-Status: No, hits=-0.6 required=5.0 tests=AWL,BAYES_00,DKIM_ADSP_CUSTOM_MED,FREEMAIL_FROM,NML_ADSP_CUSTOM_MED,SPF_HELO_PASS,T_RP_MATCHES_RCVD,T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from kuber.nabble.com (HELO kuber.nabble.com) (216.139.236.158) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 06 May 2010 09:08:16 +0000 Received: from isper.nabble.com ([192.168.236.156]) by kuber.nabble.com with esmtp (Exim 4.63) (envelope-from ) id 1O9x42-0003LT-EW for gcc@gcc.gnu.org; Thu, 06 May 2010 02:08:14 -0700 Message-ID: <28471097.post@talk.nabble.com> Date: Thu, 06 May 2010 09:08:00 -0000 From: yazdanbakhsh To: gcc@gcc.gnu.org Subject: Re: Question about Machine Description In-Reply-To: <28449607.post@talk.nabble.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit References: <63281.24.163.112.200.1128386718.squirrel@webmail.ncsu.edu> <28433505.post@talk.nabble.com> <28439702.post@talk.nabble.com> <28447744.post@talk.nabble.com> <28449607.post@talk.nabble.com> X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2010-05/txt/msg00092.txt.bz2 Hi, As I told I want to add "ble" intruction in MIPS that works like "beq". I used from the available branch_equality instruction that shows in the following paragraph: -------------------------------------------------------------------------------------------------- (define_insn "branch_equality" [(set (pc) (if_then_else (match_operator:SI 0 "equality_op" [(match_operand:SI 1 "register_operand" "d") (match_operand:SI 2 "register_operand" "d")]) (match_operand 3 "pc_or_label_operand" "") (match_operand 4 "pc_or_label_operand" "")))] "" "* { ss_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); return (operands[3] != pc_rtx) ? \"%*b%C0%?\\t%z1,%z2,%3\" : \"%*b%N0%?\\t%z1,%z2,%4\"; }" [(set_attr "type" "branch") (set_attr "mode" "none") (set_attr "length" "1")]) -------------------------------------------------------------------------------------------------- To add "ble" I changed "equality_op" in the header file to have "ble" as a acceptable operation.but it didn't work. Do u have any idea? I also saw some functions in the assembler that handle branchs. Should i changed assembler for this purpose? Best Regards yazdanbakhsh wrote: > > I have read all the documents, and changed some lines but nothing happened > :( > > Ian Lance Taylor-3 wrote: >> >> yazdanbakhsh writes: >> >>> I want to change instruction blez to ble. ble compare two registers and >>> jump >>> to the target address if the condition is true. >> >> Read the internals manual to understand how operand predicates and >> constraints work. See the hundreds of existing examples. Ask if you >> have specific questions. >> >> Ian >> >>> Ian Lance Taylor-3 wrote: >>>> >>>> yazdanbakhsh writes: >>>> >>>>> Please assume I'm working with the MIPS. There is a little difference >>>>> between the MIPS and what I'm actually working on it. How can I remove >>>>> immediate logical shift right/left from the compiler? >>>>> I mean If I want the programmer writes an immediate shift, It is >>>>> compiled >>>>> to >>>>> the two instructions: >>>>> >>>>> sll %2,%2,5 >>>>> >>>>> changed to: >>>>> >>>>> addi %3,%0,5 >>>>> sllv %2,%2,%3 >>>> >>>> Find the insn which generates sll. Change the operand constraints and >>>> predicates to reject an immediate operand. >>>> >>>> E.g., in mips.md this is: >>>> >>>> (define_insn "*3" >>>> [(set (match_operand:GPR 0 "register_operand" "=d") >>>> (any_shift:GPR (match_operand:GPR 1 "register_operand" "d") >>>> (match_operand:SI 2 "arith_operand" "dI")))] >>>> "!TARGET_MIPS16" >>>> { >>>> if (CONST_INT_P (operands[2])) >>>> operands[2] = GEN_INT (INTVAL (operands[2]) >>>> & (GET_MODE_BITSIZE (mode) - 1)); >>>> >>>> return "\t%0,%1,%2"; >>>> } >>>> [(set_attr "type" "shift") >>>> (set_attr "mode" "")]) >>>> >>>> >>>> For operand 2, change the predicate to register_operand and remove the >>>> 'I' constraint. >>>> >>>> Ian >>>> >>>> >>> >>> -- >>> View this message in context: >>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html >>> Sent from the gcc - Dev mailing list archive at Nabble.com. >> >> > > -- View this message in context: http://old.nabble.com/Question-about-Machine-Description-tp1026428p28471097.html Sent from the gcc - Dev mailing list archive at Nabble.com.