Question about Machine Description

Question about Machine Description

[Balaji V. Iyer]

Hi all,
   I am currently developing a GCC port for my own generic 32 bit
processor. I have this following error when I tried to compile a
benchmark.

(insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
                (const_int -137 [0xffffff77])) [72 S1 A8])
        (le:BI (reg:SI 12 r12)
            (const_int 0 [0x0]))) 0 {*cmpsi_normal}
(insn_list:REG_DEP_TRUE 86 (
nil))
    (nil))
convolve.c:236: internal compiler error: in reload_cse_simplify_operands,
at postreload.c:391
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://gcc.gnu.org/bugs.html> for instructions.
make: *** [convolve.o] Error 1

My question is that..what is the constaint/instruction I am missing? If
you could give me an assembly example tto illustrate an instrction that I
hvaent implemented, it would be nice too.

Any Help is highly appreciated.

Thanking You,

Yours Sincerely,

Balaji V. Iyer.

PS. Please CC me since I am not a subscribed member of this list.

Re: Question about Machine Description

[Ian Lance Taylor]

"Balaji V. Iyer" <bviyer@ncsu.edu> writes:

No need to send to both gcc@gcc.gnu.org and gcc-help@gcc.gnu.org.  I
removed gcc-help in this reply.  Thanks.

>    I am currently developing a GCC port for my own generic 32 bit
> processor. I have this following error when I tried to compile a
> benchmark.
> 
> (insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
>                 (const_int -137 [0xffffff77])) [72 S1 A8])
>         (le:BI (reg:SI 12 r12)
>             (const_int 0 [0x0]))) 0 {*cmpsi_normal}
> (insn_list:REG_DEP_TRUE 86 (
> nil))
>     (nil))
> convolve.c:236: internal compiler error: in reload_cse_simplify_operands,
> at postreload.c:391
> Please submit a full bug report,
> with preprocessed source if appropriate.
> See <URL:http://gcc.gnu.org/bugs.html> for instructions.
> make: *** [convolve.o] Error 1
> 
> My question is that..what is the constaint/instruction I am missing? If
> you could give me an assembly example tto illustrate an instrction that I
> hvaent implemented, it would be nice too.

This kind of error generally means that the operand predicate accepts
an operand which no constraint matches.  If the predicate (e.g.,
register_operand) accepts an operand, then there must be a constraint
that matches it.  Otherwise you will get an error in
constrain_operands, such as the above.

Ian

Re: Question about Machine Description

[Balaji V. Iyer]

Thank you very much Ian and Shreyas for your quick response. So I guess,
my question now would be, what would be an exmple that matches this
constraint below?

((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
                (const_int -137 [0xffffff77])) [72 S1 A8])
         (le:BI (reg:SI 12 r12)
            (const_int 0 [0x0]))) 0 {*cmpsi_normal}
 (insn_list:REG_DEP_TRUE 86 (
 nil))
    (nil))


The reason I ask is that, from my understanding it needs an instruction
that does the following:

   if (r12 <= 0) then
      (r2+ -137)  = 1
   else
      (r2+ -137) = 0

Is this correct?


Thanks,

Balaji V. Iyer.

PS. I am sorry for posting in both the mailing list.




Ian Lance Taylor wrote:
> "Balaji V. Iyer" <bviyer@ncsu.edu> writes:
>
> No need to send to both gcc@gcc.gnu.org and gcc-help@gcc.gnu.org.  I
> removed gcc-help in this reply.  Thanks.
>
>>    I am currently developing a GCC port for my own generic 32 bit
>> processor. I have this following error when I tried to compile a
>> benchmark.
>>
>> (insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
>>                 (const_int -137 [0xffffff77])) [72 S1 A8])
>>         (le:BI (reg:SI 12 r12)
>>             (const_int 0 [0x0]))) 0 {*cmpsi_normal}
>> (insn_list:REG_DEP_TRUE 86 (
>> nil))
>>     (nil))
>> convolve.c:236: internal compiler error: in
>> reload_cse_simplify_operands,
>> at postreload.c:391
>> Please submit a full bug report,
>> with preprocessed source if appropriate.
>> See <URL:http://gcc.gnu.org/bugs.html> for instructions.
>> make: *** [convolve.o] Error 1
>>
>> My question is that..what is the constaint/instruction I am missing? If
>> you could give me an assembly example tto illustrate an instrction that
>> I
>> hvaent implemented, it would be nice too.
>
> This kind of error generally means that the operand predicate accepts
> an operand which no constraint matches.  If the predicate (e.g.,
> register_operand) accepts an operand, then there must be a constraint
> that matches it.  Otherwise you will get an error in
> constrain_operands, such as the above.
>
> Ian
>

Re: Question about Machine Description

[Ian Lance Taylor]

"Balaji V. Iyer" <bviyer@ncsu.edu> writes:

> Thank you very much Ian and Shreyas for your quick response. So I guess,
> my question now would be, what would be an exmple that matches this
> constraint below?
> 
> ((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
>                 (const_int -137 [0xffffff77])) [72 S1 A8])
>          (le:BI (reg:SI 12 r12)
>             (const_int 0 [0x0]))) 0 {*cmpsi_normal}
>  (insn_list:REG_DEP_TRUE 86 (
>  nil))
>     (nil))

I don't think that question makes sense, at least not without more
context.

A constraint is one of the letters which appears after the operand
predicate in the .md file.  For example, in 

(define_insn "*cmpsi_ccno_1"
  [(set (reg FLAGS_REG)
	(compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
		 (match_operand:SI 1 "const0_operand" "n,n")))]
  "ix86_match_ccmode (insn, CCNOmode)"
  "@
   test{l}\t{%0, %0|%0, %0}
   cmp{l}\t{%1, %0|%0, %1}"
  [(set_attr "type" "test,icmp")
   (set_attr "length_immediate" "0,1")
   (set_attr "mode" "SI")])

there are two alternative; the constraints on operand 0 are "r" for
the first alternative and "?mr" for the second, and the constraints on
operand 1 is "n" for both alternatives.  The operand predicates are
nonimmediate_operand for operand 0 and const0_operand for operand 1.

When I said this:

> > This kind of error generally means that the operand predicate accepts
> > an operand which no constraint matches.  If the predicate (e.g.,
> > register_operand) accepts an operand, then there must be a constraint
> > that matches it.  Otherwise you will get an error in
> > constrain_operands, such as the above.

I mean that, in the instruction above, any operand which matches
nonimmediate_operand must be matched by at least one of the
constraints 'm' or 'r', and any operand which matches const0_operand
must match the constraint 'n'.

Ian

Re: Question about Machine Description

[Richard Sandiford]

Ian Lance Taylor <ian@airs.com> writes:
> This kind of error generally means that the operand predicate accepts
> an operand which no constraint matches.  If the predicate (e.g.,
> register_operand) accepts an operand, then there must be a constraint
> that matches it.  Otherwise you will get an error in
> constrain_operands, such as the above.

and later:

> When I said this:
>
>> > This kind of error generally means that the operand predicate accepts
>> > an operand which no constraint matches.  If the predicate (e.g.,
>> > register_operand) accepts an operand, then there must be a constraint
>> > that matches it.  Otherwise you will get an error in
>> > constrain_operands, such as the above.
>
> I mean that, in the instruction above, any operand which matches
> nonimmediate_operand must be matched by at least one of the
> constraints 'm' or 'r', and any operand which matches const0_operand
> must match the constraint 'n'.

This might confuse people.  It sounds your first quote is saying that
everything accepted by a predicate must also match at least one
constraint, and of course that isn't true.  E.g. register_operand
accepts registers from any class, whereas 'r' only matches GENERAL_REGS.
And it's usually OK (but not good practice, because it generates poor
code) for a nonimmediate_operand to only provide 'r' constraints.
More realistically, it's OK for a nonimmediate_operand to only allow
memory constraints for some combinations of operands.  It's reload's
job to fix this sort thing.

I realise I'm not telling you (Ian) anything new here, I just
thought it was worth clarifying.

Richard

Re: Question about Machine Description

[yazdanbakhsh]

Dear all,

I'm working on my a gcc compiler for my own written processor with the help
of SimpleScalar.
I want to remove "srav/slav" (immediate arithmetic shift) from the
instruction set. I explore ss.md file but I didn't see any define_ins for
the mentioned instructions, but they are used in other instruction
definitions.
It is also exist for addi/addui. Where I can find the definitions of these
instructions? I want to force gcc to just use register shift and register
add.

Best Regards,
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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> I'm working on my a gcc compiler for my own written processor with the help
> of SimpleScalar.
> I want to remove "srav/slav" (immediate arithmetic shift) from the
> instruction set. I explore ss.md file but I didn't see any define_ins for
> the mentioned instructions, but they are used in other instruction
> definitions.
> It is also exist for addi/addui. Where I can find the definitions of these
> instructions? I want to force gcc to just use register shift and register
> add.

There is no ss.md file in the standard gcc distribution.  If
SimpleScalar has a gcc port, I don't know anything about it.  So it's
hard to answer to your question precisely.

Instructions can come from either a .md file or a .c file in the
config/CPU directory used for your CPU.  If those instructions are
appearing in the generated assembler, then they must be in there
somewhere.

Ian

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

Please assume I'm working with the MIPS. There is a little difference
between the MIPS and what I'm actually working on it. How can I remove
immediate logical shift right/left from the compiler?
I mean If I want the programmer writes an immediate shift, It is compiled to
the two instructions:

sll %2,%2,5

changed to:

addi %3,%0,5
sllv %2,%2,%3

thanks in advance

Ian Lance Taylor-3 wrote:
> 
> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
> 
>> I'm working on my a gcc compiler for my own written processor with the
>> help
>> of SimpleScalar.
>> I want to remove "srav/slav" (immediate arithmetic shift) from the
>> instruction set. I explore ss.md file but I didn't see any define_ins for
>> the mentioned instructions, but they are used in other instruction
>> definitions.
>> It is also exist for addi/addui. Where I can find the definitions of
>> these
>> instructions? I want to force gcc to just use register shift and register
>> add.
> 
> There is no ss.md file in the standard gcc distribution.  If
> SimpleScalar has a gcc port, I don't know anything about it.  So it's
> hard to answer to your question precisely.
> 
> Instructions can come from either a .md file or a .c file in the
> config/CPU directory used for your CPU.  If those instructions are
> appearing in the generated assembler, then they must be in there
> somewhere.
> 
> Ian
> 
> 

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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> Please assume I'm working with the MIPS. There is a little difference
> between the MIPS and what I'm actually working on it. How can I remove
> immediate logical shift right/left from the compiler?
> I mean If I want the programmer writes an immediate shift, It is compiled to
> the two instructions:
>
> sll %2,%2,5
>
> changed to:
>
> addi %3,%0,5
> sllv %2,%2,%3

Find the insn which generates sll.  Change the operand constraints and
predicates to reject an immediate operand.

E.g., in mips.md this is:

(define_insn "*<optab><mode>3"
  [(set (match_operand:GPR 0 "register_operand" "=d")
	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
		       (match_operand:SI 2 "arith_operand" "dI")))]
  "!TARGET_MIPS16"
{
  if (CONST_INT_P (operands[2]))
    operands[2] = GEN_INT (INTVAL (operands[2])
			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));

  return "<d><insn>\t%0,%1,%2";
}
  [(set_attr "type" "shift")
   (set_attr "mode" "<MODE>")])


For operand 2, change the predicate to register_operand and remove the
'I' constraint.

Ian

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

I want to change instruction blez to ble. ble compare two registers and jump
to the target address if the condition is true.

thanks in advance,

Ian Lance Taylor-3 wrote:
> 
> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
> 
>> Please assume I'm working with the MIPS. There is a little difference
>> between the MIPS and what I'm actually working on it. How can I remove
>> immediate logical shift right/left from the compiler?
>> I mean If I want the programmer writes an immediate shift, It is compiled
>> to
>> the two instructions:
>>
>> sll %2,%2,5
>>
>> changed to:
>>
>> addi %3,%0,5
>> sllv %2,%2,%3
> 
> Find the insn which generates sll.  Change the operand constraints and
> predicates to reject an immediate operand.
> 
> E.g., in mips.md this is:
> 
> (define_insn "*<optab><mode>3"
>   [(set (match_operand:GPR 0 "register_operand" "=d")
> 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
> 		       (match_operand:SI 2 "arith_operand" "dI")))]
>   "!TARGET_MIPS16"
> {
>   if (CONST_INT_P (operands[2]))
>     operands[2] = GEN_INT (INTVAL (operands[2])
> 			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));
> 
>   return "<d><insn>\t%0,%1,%2";
> }
>   [(set_attr "type" "shift")
>    (set_attr "mode" "<MODE>")])
> 
> 
> For operand 2, change the predicate to register_operand and remove the
> 'I' constraint.
> 
> Ian
> 
> 

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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> I want to change instruction blez to ble. ble compare two registers and jump
> to the target address if the condition is true.

Read the internals manual to understand how operand predicates and
constraints work.  See the hundreds of existing examples.  Ask if you
have specific questions.

Ian

> Ian Lance Taylor-3 wrote:
>> 
>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>> 
>>> Please assume I'm working with the MIPS. There is a little difference
>>> between the MIPS and what I'm actually working on it. How can I remove
>>> immediate logical shift right/left from the compiler?
>>> I mean If I want the programmer writes an immediate shift, It is compiled
>>> to
>>> the two instructions:
>>>
>>> sll %2,%2,5
>>>
>>> changed to:
>>>
>>> addi %3,%0,5
>>> sllv %2,%2,%3
>> 
>> Find the insn which generates sll.  Change the operand constraints and
>> predicates to reject an immediate operand.
>> 
>> E.g., in mips.md this is:
>> 
>> (define_insn "*<optab><mode>3"
>>   [(set (match_operand:GPR 0 "register_operand" "=d")
>> 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>> 		       (match_operand:SI 2 "arith_operand" "dI")))]
>>   "!TARGET_MIPS16"
>> {
>>   if (CONST_INT_P (operands[2]))
>>     operands[2] = GEN_INT (INTVAL (operands[2])
>> 			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));
>> 
>>   return "<d><insn>\t%0,%1,%2";
>> }
>>   [(set_attr "type" "shift")
>>    (set_attr "mode" "<MODE>")])
>> 
>> 
>> For operand 2, change the predicate to register_operand and remove the
>> 'I' constraint.
>> 
>> Ian
>> 
>> 
>
> -- 
> View this message in context: http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html
> Sent from the gcc - Dev mailing list archive at Nabble.com.

Re: Question about Machine Description

[yazdanbakhsh]

I have read all the documents, and changed some lines but nothing happened :(

Ian Lance Taylor-3 wrote:
> 
> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
> 
>> I want to change instruction blez to ble. ble compare two registers and
>> jump
>> to the target address if the condition is true.
> 
> Read the internals manual to understand how operand predicates and
> constraints work.  See the hundreds of existing examples.  Ask if you
> have specific questions.
> 
> Ian
> 
>> Ian Lance Taylor-3 wrote:
>>> 
>>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>>> 
>>>> Please assume I'm working with the MIPS. There is a little difference
>>>> between the MIPS and what I'm actually working on it. How can I remove
>>>> immediate logical shift right/left from the compiler?
>>>> I mean If I want the programmer writes an immediate shift, It is
>>>> compiled
>>>> to
>>>> the two instructions:
>>>>
>>>> sll %2,%2,5
>>>>
>>>> changed to:
>>>>
>>>> addi %3,%0,5
>>>> sllv %2,%2,%3
>>> 
>>> Find the insn which generates sll.  Change the operand constraints and
>>> predicates to reject an immediate operand.
>>> 
>>> E.g., in mips.md this is:
>>> 
>>> (define_insn "*<optab><mode>3"
>>>   [(set (match_operand:GPR 0 "register_operand" "=d")
>>> 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>>> 		       (match_operand:SI 2 "arith_operand" "dI")))]
>>>   "!TARGET_MIPS16"
>>> {
>>>   if (CONST_INT_P (operands[2]))
>>>     operands[2] = GEN_INT (INTVAL (operands[2])
>>> 			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));
>>> 
>>>   return "<d><insn>\t%0,%1,%2";
>>> }
>>>   [(set_attr "type" "shift")
>>>    (set_attr "mode" "<MODE>")])
>>> 
>>> 
>>> For operand 2, change the predicate to register_operand and remove the
>>> 'I' constraint.
>>> 
>>> Ian
>>> 
>>> 
>>
>> -- 
>> View this message in context:
>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html
>> Sent from the gcc - Dev mailing list archive at Nabble.com.
> 
> 

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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> I have read all the documents, and changed some lines but nothing happened :(

That is good, but to get help you really need to ask specific
questions.  Show us an insn pattern, tell us what you are trying to
do, tell us what you did, tell us what happened.

Ian

> Ian Lance Taylor-3 wrote:
>> 
>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>> 
>>> I want to change instruction blez to ble. ble compare two registers and
>>> jump
>>> to the target address if the condition is true.
>> 
>> Read the internals manual to understand how operand predicates and
>> constraints work.  See the hundreds of existing examples.  Ask if you
>> have specific questions.
>> 
>> Ian
>> 
>>> Ian Lance Taylor-3 wrote:
>>>> 
>>>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>>>> 
>>>>> Please assume I'm working with the MIPS. There is a little difference
>>>>> between the MIPS and what I'm actually working on it. How can I remove
>>>>> immediate logical shift right/left from the compiler?
>>>>> I mean If I want the programmer writes an immediate shift, It is
>>>>> compiled
>>>>> to
>>>>> the two instructions:
>>>>>
>>>>> sll %2,%2,5
>>>>>
>>>>> changed to:
>>>>>
>>>>> addi %3,%0,5
>>>>> sllv %2,%2,%3
>>>> 
>>>> Find the insn which generates sll.  Change the operand constraints and
>>>> predicates to reject an immediate operand.
>>>> 
>>>> E.g., in mips.md this is:
>>>> 
>>>> (define_insn "*<optab><mode>3"
>>>>   [(set (match_operand:GPR 0 "register_operand" "=d")
>>>> 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>>>> 		       (match_operand:SI 2 "arith_operand" "dI")))]
>>>>   "!TARGET_MIPS16"
>>>> {
>>>>   if (CONST_INT_P (operands[2]))
>>>>     operands[2] = GEN_INT (INTVAL (operands[2])
>>>> 			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));
>>>> 
>>>>   return "<d><insn>\t%0,%1,%2";
>>>> }
>>>>   [(set_attr "type" "shift")
>>>>    (set_attr "mode" "<MODE>")])
>>>> 
>>>> 
>>>> For operand 2, change the predicate to register_operand and remove the
>>>> 'I' constraint.
>>>> 
>>>> Ian
>>>> 
>>>> 
>>>
>>> -- 
>>> View this message in context:
>>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html
>>> Sent from the gcc - Dev mailing list archive at Nabble.com.
>> 
>> 
>
> -- 
> View this message in context: http://old.nabble.com/Question-about-Machine-Description-tp1026428p28449607.html
> Sent from the gcc - Dev mailing list archive at Nabble.com.

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

I changed the .md and .c file:

I add these lines to the .md file:

-----------------------------------------------------------------
(define_insn "ble1"
  [(set (pc)
	(if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:SI 1 "register_operand" "=d,d"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "ble1\\t%0,%1,%2"

 [(set_attr "type" "branch")
  (set_attr "mode" "SI")])

(define_expand "cbranchsi4"
  [(set (pc)
	(if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:SI 1 "register_operand" "=d,d"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "
{
      gen_conditional_le (operands[0],operands[1],operands[2]);
      DONE;
}")
-----------------------------------------------------------------

and add these lines to the .c file:

***************************************************
gen_conditional_le(rtx comp1, rtx comp2, rtx final_label)
{
printf("my operation called");
emit_insn(gen_ble1(comp1, comp2, final_label));
return TRUE;
}
***************************************************

but it didn't work...
I want the following C code is compiled to just one instruction:

if(a<=b)
      c = 10;

asembly:
     ble1 $1,$2,0x...

(a ===> $1 and b===> $2)

I appreciate it if you would guide me through this issue.

best regards

Ian Lance Taylor-3 wrote:
> 
> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
> 
>> I have read all the documents, and changed some lines but nothing
>> happened :(
> 
> That is good, but to get help you really need to ask specific
> questions.  Show us an insn pattern, tell us what you are trying to
> do, tell us what you did, tell us what happened.
> 
> Ian
> 
>> Ian Lance Taylor-3 wrote:
>>> 
>>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>>> 
>>>> I want to change instruction blez to ble. ble compare two registers and
>>>> jump
>>>> to the target address if the condition is true.
>>> 
>>> Read the internals manual to understand how operand predicates and
>>> constraints work.  See the hundreds of existing examples.  Ask if you
>>> have specific questions.
>>> 
>>> Ian
>>> 
>>>> Ian Lance Taylor-3 wrote:
>>>>> 
>>>>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>>>>> 
>>>>>> Please assume I'm working with the MIPS. There is a little difference
>>>>>> between the MIPS and what I'm actually working on it. How can I
>>>>>> remove
>>>>>> immediate logical shift right/left from the compiler?
>>>>>> I mean If I want the programmer writes an immediate shift, It is
>>>>>> compiled
>>>>>> to
>>>>>> the two instructions:
>>>>>>
>>>>>> sll %2,%2,5
>>>>>>
>>>>>> changed to:
>>>>>>
>>>>>> addi %3,%0,5
>>>>>> sllv %2,%2,%3
>>>>> 
>>>>> Find the insn which generates sll.  Change the operand constraints and
>>>>> predicates to reject an immediate operand.
>>>>> 
>>>>> E.g., in mips.md this is:
>>>>> 
>>>>> (define_insn "*<optab><mode>3"
>>>>>   [(set (match_operand:GPR 0 "register_operand" "=d")
>>>>> 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>>>>> 		       (match_operand:SI 2 "arith_operand" "dI")))]
>>>>>   "!TARGET_MIPS16"
>>>>> {
>>>>>   if (CONST_INT_P (operands[2]))
>>>>>     operands[2] = GEN_INT (INTVAL (operands[2])
>>>>> 			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));
>>>>> 
>>>>>   return "<d><insn>\t%0,%1,%2";
>>>>> }
>>>>>   [(set_attr "type" "shift")
>>>>>    (set_attr "mode" "<MODE>")])
>>>>> 
>>>>> 
>>>>> For operand 2, change the predicate to register_operand and remove the
>>>>> 'I' constraint.
>>>>> 
>>>>> Ian
>>>>> 
>>>>> 
>>>>
>>>> -- 
>>>> View this message in context:
>>>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html
>>>> Sent from the gcc - Dev mailing list archive at Nabble.com.
>>> 
>>> 
>>
>> -- 
>> View this message in context:
>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28449607.html
>> Sent from the gcc - Dev mailing list archive at Nabble.com.
> 
> 

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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> (define_expand "cbranchsi4"
>   [(set (pc)
> 	(if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
> (match_operand:SI 1 "register_operand" "=d,d"))
> 		      (label_ref (match_operand 2 "" ""))
> 		      (pc)))]
>   ""
>   "
> {
>       gen_conditional_le (operands[0],operands[1],operands[2]);
>       DONE;
> }")

The cbranchsi4 expander will be called to generate all conditional
branches.  You are only generating a ble, which is not going work.
The insn pattern of an expander is simply the default insn that it
generates.  When you end the expander code with DONE, the insn pattern
is ignored.  If you want to take this approach you need to handle all
supported conditional branches here.

See many examples in existing backends.  Besides the extensive
internal documentation, there are dozens of working examples that you
can look at to see how to implement this.


> but it didn't work...

In your next message please tell us how it failed, not merely the fact
that it failed.

Ian

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

I found an strategy that would solve my problem.
I changed .md with the following paragraph...

--------------------------------------------------------------------------------------------

(define_expand "blt"
  [(set (pc)
	(if_then_else (lt:SI (match_dup 1)
			           (match_dup 2))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
	operands[1] = branch_cmp[0];
	operands[2] = branch_cmp[1];
}")

(define_insn "*bltdf"
  [(set (pc)
	(if_then_else (lt:SI (match_operand:DF 1 "" "")
			     (match_operand:DF 2 "" ""))
	(match_operand 3 "pc_or_label_operand" "")
	(match_operand 4 "pc_or_label_operand" "")))]
  ""

  "*
{
  ss_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
  return (operands[3] != pc_rtx)
	? \"blt\\t%z1,%z2,%3\"
	: \"blt\\t%z1,%z2,%4\";
}"
)

(define_insn "*bltdi"
  [(set (pc)
	(if_then_else (lt:SI (match_operand:DI 1 "" "")
			     (match_operand:DI 2 "" ""))
	(match_operand 3 "pc_or_label_operand" "")
	(match_operand 4 "pc_or_label_operand" "")))]
  ""

  "*
{
  ss_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
  return (operands[3] != pc_rtx)
	? \"blt\\t%z1,%z2,%3\"
	: \"blt\\t%z1,%z2,%4\";
}"
)

(define_insn "*bltsi"
  [(set (pc)
	(if_then_else (lt:SI (match_operand:SI 1 "" "")
			     (match_operand:SI 2 "" ""))
	(match_operand 3 "pc_or_label_operand" "")
	(match_operand 4 "pc_or_label_operand" "")))]
  ""

  "*
{
  ss_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
  return (operands[3] != pc_rtx)
	? \"blt\\t%z1,%z2,%3\"
	: \"blt\\t%z1,%z2,%4\";
}"
)
--------------------------------------------------------------------------------------------
and add the following line to the mips-opc.c:

{"blt",     "s,t,p",	0x0000000d, 0x0000ffff,	        0	        },

but during cmpilation, I encounter the following error:
...
_ashrdi3
_ffsdi2
_udiv_w_sdiv
_udivmoddi4
_cmpdi2
_ucmpdi2
_floatdidf
_floatdisf
_fixunsdfsi
_fixunssfsi
_fixunsdfdi
/tmp/ccrWquNC.s: Assembler messages:
/tmp/ccrWquNC.s:169: Error: illegal operands `blt'
/tmp/ccrWquNC.s:231: Error: illegal operands `blt'
make: *** [libgcc2.a] Error 1


I appreciate any help...


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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> (define_insn "*bltdf"
>   [(set (pc)
> 	(if_then_else (lt:SI (match_operand:DF 1 "" "")
> 			     (match_operand:DF 2 "" ""))
> 	(match_operand 3 "pc_or_label_operand" "")
> 	(match_operand 4 "pc_or_label_operand" "")))]
>   ""
>
>   "*
> {
>   ss_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
>   return (operands[3] != pc_rtx)
> 	? \"blt\\t%z1,%z2,%3\"
> 	: \"blt\\t%z1,%z2,%4\";
> }"
> )

This define_insn looks wrong.  There are no operand predicates.  There
are no operand constraints.  A define_expand does not need those; a
define_insn does.


> _fixunsdfdi
> /tmp/ccrWquNC.s: Assembler messages:
> /tmp/ccrWquNC.s:169: Error: illegal operands `blt'
> /tmp/ccrWquNC.s:231: Error: illegal operands `blt'
> make: *** [libgcc2.a] Error 1

If you look carefully at the make log, you will see the compilation
command that is being run.  Run that command with the --save-temps
option.  Look at the resulting libgcc2.s file.  Make sure the blt
instructions looks right.

I assume that you have tested your assembler to confirm that it
handles blt as you want it to.

Ian

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

I want to exclude XORI from the instruction set of a cpu. I deleted all the
XORI in md file. But when I compiled my program some XORI operation still
exist. how this would be possible?
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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> I want to exclude XORI from the instruction set of a cpu. I deleted all the
> XORI in md file. But when I compiled my program some XORI operation still
> exist. how this would be possible?

It could be printed directly from a .c file in your config/CPU
directory.

Ian

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

I want to exclude all immediate or instruction. I did this by the following
define_insn

/------------------------------------------------------------------------------
(define_insn "iorsi3" 
  [(set (match_operand:SI 0 "register_operand" "=d,d")
	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
		(match_operand:SI 2 "uns_arith_operand" "d,K")))
		(clobber (match_scratch:SI 3 ""))]
  ""
  "@
   or\\t%0,%1,%2
   addi\\t%3,0x0,%x2\;or\\t%0,%1,%3"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")
   (set_attr "length"	"1,2")])
/------------------------------------------------------------------------------
I use a temporary register 3, to store intermediate values. but after
compilation the following error happen:

./libgcc2.c:669: internal error--unrecognizable insn:
(insn 787 786 780 (set (reg:SI 104)
        (ior:SI (reg:SI 104)
            (const_int 65535))) -1 (insn_list 786 (nil))
    (expr_list:REG_EQUAL (const_int 16777215)
        (nil)))
xgcc: Internal compiler error: program cc1 got fatal signal 6
make: *** [libgcc2.a] Error 1
//----------------------------------------------------------------------
I appreciate any help.

Bestr
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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> I want to exclude all immediate or instruction. I did this by the following
> define_insn
>
> /------------------------------------------------------------------------------
> (define_insn "iorsi3" 
>   [(set (match_operand:SI 0 "register_operand" "=d,d")
> 	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
> 		(match_operand:SI 2 "uns_arith_operand" "d,K")))
> 		(clobber (match_scratch:SI 3 ""))]
>   ""
>   "@
>    or\\t%0,%1,%2
>    addi\\t%3,0x0,%x2\;or\\t%0,%1,%3"
>   [(set_attr "type"	"arith")
>    (set_attr "mode"	"SI")
>    (set_attr "length"	"1,2")])
> /------------------------------------------------------------------------------


No need for that, reload will do the work for you.  Just remove the
second alternative entirely.

(define_insn "iorsi3" 
  [(set (match_operand:SI 0 "register_operand" "=d")
	(ior:SI (match_operand:SI 1 "register_operand" "%d")
		(match_operand:SI 2 "register_operand" "d")))]
  ""
  "or\\t%0,%1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")
   (set_attr "length"	"1")])


By the way, in your define_insn you omitted the constraints from your
match_scratch.  I'm surprised it worked at all.  You should have used
"X,d".


> I use a temporary register 3, to store intermediate values. but after
> compilation the following error happen:
>
> ./libgcc2.c:669: internal error--unrecognizable insn:
> (insn 787 786 780 (set (reg:SI 104)
>         (ior:SI (reg:SI 104)
>             (const_int 65535))) -1 (insn_list 786 (nil))
>     (expr_list:REG_EQUAL (const_int 16777215)
>         (nil)))
> xgcc: Internal compiler error: program cc1 got fatal signal 6
> make: *** [libgcc2.a] Error 1

There is no clobber there, so the pattern doesn't match.  You would
have to find out what generated that insn.  It didn't come from the
usual path, which would be to call gen_iorsi3.  It must have come from
a define_expand or directly from C code.

Ian

Re: Question about Machine Description

[yazdanbakhsh]

I did what you said, and the same error happened :(
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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> I did what you said, and the same error happened :(

I'm sorry you're having trouble, but if you want us to be able to help
you you need to show us precisely what you did, precisely what
happened, and what you expected to happen.

Ian

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

I want to limit the size of immediate field of some operation. For example
somehow modify the machine description that the compiler supports only 0-255
for immediate operand.
I also want to change the compiler to the 2-address operand.
do you have any ideas?
I just need some hint

Best Regards,
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Re: Question about Machine Description

[Revital1 Eres]

Hello,

> I want to limit the size of immediate field of some operation.

I think you can look at SIGNED_INT_FITS_N_BITS definition at
config/crx/crx.c
for such example.
You can write a predicate like the following; and use it when describing
the immediate
operand in the md file.

(define_predicate "s24bits_operand"
  (match_code "const_int")
  {
    return (SIGNED_INT_FITS_N_BITS(INTVAL(op), 24)) ? 1 : 0;
  }
)

Thanks,
Revital

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

I'm working with GCC 2.7. I think, It doesn't support define_predict.
I define a c function in the mips.c file and add the following lines:

int
new_arith_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == CONST_INT)
	if(NEW_INT_UNSIGNED (op))
	    return TRUE;
	else
	    return FALSE;

  return register_operand (op, mode);
}

I use the name of this function to check the value of the input operand.
When I compile the gcc the following error happens:

./libgcc2.c: In function `__divdi3':
./libgcc2.c:669: internal error--unrecognizable insn:
(insn 787 786 780 (set (reg:SI 104)
        (ior:SI (reg:SI 104)
            (const_int 65535))) -1 (insn_list 786 (nil))
    (expr_list:REG_EQUAL (const_int 16777215)
        (nil)))


I appreciate any help.

Regards
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Re: Question about Machine Description

[Manuel López-Ibáñez]

On 15 June 2010 14:01, yazdanbakhsh <amir.yazdanbakhsh@gmail.com> wrote:
>
> I'm working with GCC 2.7. I think, It doesn't support define_predict.
> I define a c function in the mips.c file and add the following lines:
[...]
> I appreciate any help.

I think the best advice I can give you is: Use a recent GCC version.
GCC 2.7 is almost 10 years old.

Manuel.

Re: Question about Machine Description

[yazdanbakhsh]

Actually, I'm working with simplescalar and it only supports gcc 2.9.
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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> I'm working with GCC 2.7.

I think I see your problem.


> I think, It doesn't support define_predict.
> I define a c function in the mips.c file and add the following lines:
>
> int
> new_arith_operand (op, mode)
>      rtx op;
>      enum machine_mode mode;
> {
>   if (GET_CODE (op) == CONST_INT)
> 	if(NEW_INT_UNSIGNED (op))
> 	    return TRUE;
> 	else
> 	    return FALSE;
>
>   return register_operand (op, mode);
> }
>
> I use the name of this function to check the value of the input operand.
> When I compile the gcc the following error happens:
>
> ./libgcc2.c: In function `__divdi3':
> ./libgcc2.c:669: internal error--unrecognizable insn:
> (insn 787 786 780 (set (reg:SI 104)
>         (ior:SI (reg:SI 104)
>             (const_int 65535))) -1 (insn_list 786 (nil))
>     (expr_list:REG_EQUAL (const_int 16777215)
>         (nil)))

Make sure your constraint characters are consistent with your
predicate.  If your constraint has an 'i', then reload won't know that
it needs to push the out-of-range constant into a register.

Ian

Re: Question about Machine Description

[yazdanbakhsh]

Hi,

As I told I want to add  "ble" intruction in MIPS that works like "beq".

I used from the available branch_equality instruction that shows in the
following paragraph:

--------------------------------------------------------------------------------------------------
(define_insn "branch_equality"
  [(set (pc)
	(if_then_else (match_operator:SI 0 "equality_op"
					 [(match_operand:SI 1 "register_operand" "d")
					  (match_operand:SI 2 "register_operand" "d")])
	(match_operand 3 "pc_or_label_operand" "")
	(match_operand 4 "pc_or_label_operand" "")))]
  ""
  "*
{
  ss_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
  return (operands[3] != pc_rtx)
	? \"%*b%C0%?\\t%z1,%z2,%3\"
	: \"%*b%N0%?\\t%z1,%z2,%4\";
}"
  [(set_attr "type"	"branch")
   (set_attr "mode"	"none")
   (set_attr "length"	"1")])
--------------------------------------------------------------------------------------------------
To add "ble" I changed "equality_op" in the header file to have "ble" as a
acceptable operation.but it didn't work. Do u have any idea? I also saw some
functions in the assembler that handle branchs. Should i changed assembler
for this purpose?

Best Regards



yazdanbakhsh wrote:
> 
> I have read all the documents, and changed some lines but nothing happened
> :(
> 
> Ian Lance Taylor-3 wrote:
>> 
>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>> 
>>> I want to change instruction blez to ble. ble compare two registers and
>>> jump
>>> to the target address if the condition is true.
>> 
>> Read the internals manual to understand how operand predicates and
>> constraints work.  See the hundreds of existing examples.  Ask if you
>> have specific questions.
>> 
>> Ian
>> 
>>> Ian Lance Taylor-3 wrote:
>>>> 
>>>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>>>> 
>>>>> Please assume I'm working with the MIPS. There is a little difference
>>>>> between the MIPS and what I'm actually working on it. How can I remove
>>>>> immediate logical shift right/left from the compiler?
>>>>> I mean If I want the programmer writes an immediate shift, It is
>>>>> compiled
>>>>> to
>>>>> the two instructions:
>>>>>
>>>>> sll %2,%2,5
>>>>>
>>>>> changed to:
>>>>>
>>>>> addi %3,%0,5
>>>>> sllv %2,%2,%3
>>>> 
>>>> Find the insn which generates sll.  Change the operand constraints and
>>>> predicates to reject an immediate operand.
>>>> 
>>>> E.g., in mips.md this is:
>>>> 
>>>> (define_insn "*<optab><mode>3"
>>>>   [(set (match_operand:GPR 0 "register_operand" "=d")
>>>> 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>>>> 		       (match_operand:SI 2 "arith_operand" "dI")))]
>>>>   "!TARGET_MIPS16"
>>>> {
>>>>   if (CONST_INT_P (operands[2]))
>>>>     operands[2] = GEN_INT (INTVAL (operands[2])
>>>> 			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));
>>>> 
>>>>   return "<d><insn>\t%0,%1,%2";
>>>> }
>>>>   [(set_attr "type" "shift")
>>>>    (set_attr "mode" "<MODE>")])
>>>> 
>>>> 
>>>> For operand 2, change the predicate to register_operand and remove the
>>>> 'I' constraint.
>>>> 
>>>> Ian
>>>> 
>>>> 
>>>
>>> -- 
>>> View this message in context:
>>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html
>>> Sent from the gcc - Dev mailing list archive at Nabble.com.
>> 
>> 
> 
> 

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Re: Question about Machine Description

[yazdanbakhsh]

Is it any way that we can chat?
I'm working on my thesis project and a paper. I appreciate it if you would
cooperate in this project.
I have gmail Id "amir.yazdanbakhsh"
and also skype "amir.yazdanbakhsh"

best regards,

yazdanbakhsh wrote:
> 
> Hi,
> 
> Please assume I'm working with the MIPS. There is a little difference
> between the MIPS and what I'm actually working on it. How can I remove
> immediate logical shift right/left from the compiler?
> I mean If I want the programmer writes an immediate shift, It is compiled
> to the two instructions:
> 
> sll %2,%2,5
> 
> changed to:
> 
> addi %3,%0,5
> sllv %2,%2,%3
> 
> thanks in advance
> 
> Ian Lance Taylor-3 wrote:
>> 
>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>> 
>>> I'm working on my a gcc compiler for my own written processor with the
>>> help
>>> of SimpleScalar.
>>> I want to remove "srav/slav" (immediate arithmetic shift) from the
>>> instruction set. I explore ss.md file but I didn't see any define_ins
>>> for
>>> the mentioned instructions, but they are used in other instruction
>>> definitions.
>>> It is also exist for addi/addui. Where I can find the definitions of
>>> these
>>> instructions? I want to force gcc to just use register shift and
>>> register
>>> add.
>> 
>> There is no ss.md file in the standard gcc distribution.  If
>> SimpleScalar has a gcc port, I don't know anything about it.  So it's
>> hard to answer to your question precisely.
>> 
>> Instructions can come from either a .md file or a .c file in the
>> config/CPU directory used for your CPU.  If those instructions are
>> appearing in the generated assembler, then they must be in there
>> somewhere.
>> 
>> Ian
>> 
>> 
> 
> 

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Re: Question about Machine Description

[yazdanbakhsh]

I forget to thank you for your help.
But if I do write your code how compiler knows that it should be put two
instructions instead immediate shift?

I write this piese of code:

###############################################################33
(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
		     (match_operand:SI 2 "arith_operand" "dI")))
	(clobber(match_scratch:SI 3 "=&d"))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))&
0x1f);
    operands[4] = gen_rtx (REG, VOIDmode, 0);
  return \"add\\t%3,%4,%z2;srl\\t%0,%1,%3\";
}"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")
   (set_attr "length"	"1")])
################################################################

Is there any other solutions?

Best Regards,

yazdanbakhsh wrote:
> 
> Is it any way that we can chat?
> I'm working on my thesis project and a paper. I appreciate it if you would
> cooperate in this project.
> I have gmail Id "amir.yazdanbakhsh"
> and also skype "amir.yazdanbakhsh"
> 
> best regards,
> 
> yazdanbakhsh wrote:
>> 
>> Hi,
>> 
>> Please assume I'm working with the MIPS. There is a little difference
>> between the MIPS and what I'm actually working on it. How can I remove
>> immediate logical shift right/left from the compiler?
>> I mean If I want the programmer writes an immediate shift, It is compiled
>> to the two instructions:
>> 
>> sll %2,%2,5
>> 
>> changed to:
>> 
>> addi %3,%0,5
>> sllv %2,%2,%3
>> 
>> thanks in advance
>> 
>> Ian Lance Taylor-3 wrote:
>>> 
>>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>>> 
>>>> I'm working on my a gcc compiler for my own written processor with the
>>>> help
>>>> of SimpleScalar.
>>>> I want to remove "srav/slav" (immediate arithmetic shift) from the
>>>> instruction set. I explore ss.md file but I didn't see any define_ins
>>>> for
>>>> the mentioned instructions, but they are used in other instruction
>>>> definitions.
>>>> It is also exist for addi/addui. Where I can find the definitions of
>>>> these
>>>> instructions? I want to force gcc to just use register shift and
>>>> register
>>>> add.
>>> 
>>> There is no ss.md file in the standard gcc distribution.  If
>>> SimpleScalar has a gcc port, I don't know anything about it.  So it's
>>> hard to answer to your question precisely.
>>> 
>>> Instructions can come from either a .md file or a .c file in the
>>> config/CPU directory used for your CPU.  If those instructions are
>>> appearing in the generated assembler, then they must be in there
>>> somewhere.
>>> 
>>> Ian
>>> 
>>> 
>> 
>> 
> 
> 

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Re: Question about Machine Description

[yazdanbakhsh]

This is the newer version. It works correctly. I just want know is there any
other way.

thanks
***************************************************
(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
		     (match_operand:SI 2 "arith_operand" "dI")))
	(clobber(match_scratch:SI 3 "=&d"))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
{
    operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))&
0x1f);
    operands[4] = gen_rtx (REG, VOIDmode, 0);
    return \"add\\t%3,%4,%z2;srl\\t%0,%1,%3\";
}
else
	return \"srl\\t%0,%1,%2\";
}"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")
   (set_attr "length"	"1")])
***************************************************

yazdanbakhsh wrote:
> 
> Dear all,
> 
> I'm working on my a gcc compiler for my own written processor with the
> help of SimpleScalar.
> I want to remove "srav/slav" (immediate arithmetic shift) from the
> instruction set. I explore ss.md file but I didn't see any define_ins for
> the mentioned instructions, but they are used in other instruction
> definitions.
> It is also exist for addi/addui. Where I can find the definitions of these
> instructions? I want to force gcc to just use register shift and register
> add.
> 
> Best Regards,
> 

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Re: Question about Machine Description

[Ian Lance Taylor]

yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:

> This is the newer version. It works correctly. I just want know is there any
> other way.

Did you read what I wrote earlier?

http://gcc.gnu.org/ml/gcc/2010-05/msg00048.html

Ian