From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31572 invoked by alias); 15 Sep 2004 18:17:15 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 31526 invoked from network); 15 Sep 2004 18:17:12 -0000 Received: from unknown (HELO ngate.noida.hcltech.com) (202.54.110.230) by sourceware.org with SMTP; 15 Sep 2004 18:17:12 -0000 Received: from noida.hcltech.com ([10.112.42.221]) by ngate.noida.hcltech.com (8.12.5/8.12.5) with ESMTP id i8FIRaE7006396 for ; Wed, 15 Sep 2004 23:57:38 +0530 Subject: PIC code for coldfire v4e MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Date: Wed, 15 Sep 2004 18:40:00 -0000 Content-class: urn:content-classes:message Message-ID: <33BC33A9E76474479B76AD0DE8A169728DD2@exch-ntd.nec.noida.hcltech.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: From: "C Jaiprakash, Noida" To: Cc: "C Jaiprakash, Noida" X-SW-Source: 2004-09/txt/msg00925.txt.bz2 Hi, I am trying to provide PIC support for coldfire v4e. Curently movsi patt= ern generates PIC code , basically it generates a RTX like PLUS(a5, symboli= c_operand) where a5 is PIC offset table pointer. And at the final assembly = o/p @GOT is appended to the symbol if base register is a5. For coldfire v4= e this can not be done because only 16 bit offset is allowed. May be someth= ing like=20 lea running@GOT.w, %register move.l (%a5,%register), %a0 instead of=20 move.l running@GOT.w(%a5),%a0 will have to be done. But i am facing implementation problems for this. I c= an not force_reg symbolic operand in "movsi" pattern. I tried to split this= later but the problem is print_operand_address relies on base register for= adding @GOT while assembly generation, which will not happen if i spilt th= e "movsi" insn. Any hint where cani do this? Below is "movsi"=20 pattern for reference.=20 (define_expand "movsi" [(set (match_operand:SI 0 "nonimmediate_operand" "") (match_operand:SI 1 "general_operand" ""))] "" " { if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode)) { /* The source is an address which requires PIC relocation. Call legitimize_pic_address with the source, mode, and a relocation register (a new pseudo, or the final destination if reload_in_prog= ress is set). Then fall through normally */ rtx temp =3D reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); operands[1] =3D legitimize_pic_address (operands[1], SImode, temp); } else if (flag_pic && TARGET_PCREL && ! reload_in_progress) { /* Don't allow writes to memory except via a register; the m68k doesn't consider PC-relative addresses to be writable. */ if (symbolic_operand (operands[0], SImode)) operands[0] =3D force_reg (SImode, XEXP (operands[0], 0)); else if (GET_CODE (operands[0]) =3D=3D MEM && symbolic_operand (XEXP (operands[0], 0), SImode)) operands[0] =3D gen_rtx (MEM, SImode, force_reg (SImode, XEXP (operands[0], 0))); } }") cj