RE: A problem with one instruction multiple latencies and pipelines

["Qian, Jianhua" <qianjh@cn.fujitsu.com>]

Hi Richard

> -----Original Message-----
> From: Richard Biener <richard.guenther@gmail.com>
> Sent: Monday, September 7, 2020 3:41 PM
> To: Qian, Jianhua/钱 建华 <qianjh@cn.fujitsu.com>
> Cc: gcc@gcc.gnu.org
> Subject: Re: A problem with one instruction multiple latencies and pipelines
> 
> On Mon, Sep 7, 2020 at 8:10 AM Qian, Jianhua <qianjh@cn.fujitsu.com> wrote:
> >
> > Hi
> >
> > I'm adding a new machine model. I have a problem when writing the
> "define_insn_reservation" for instruction scheduling.
> > How to write the "define_insn_reservation" for one instruction that there are
> different latencies and pipelines according to parameter.
> >
> > For example, the ADD (shifted register) instruction in a64fx
> >
> > Instruction            Option                             Latency
> Pipeline
> > ADD (shifted register)  <amount> = 0                     1          EX*
> | EAG*
> >                       <amount> = [1-4] && <shift>=LSL  1+1
> (EXA + EXA) | (EXB + EXB)
> >                                                          2+1       (EXA
> + EXA) | (EXB + EXB)
> >
> > In aarch64.md ADD (shifted register) instruction is defined as following．
> >  (define_insn "*add_<shift>_<mode>"
> >   [(set (match_operand:GPI 0 "register_operand" "=r")
> >         (plus:GPI (ASHIFT:GPI (match_operand:GPI 1 "register_operand"
> "r")
> >                               (match_operand:QI 2
> "aarch64_shift_imm_<mode>" "n"))
> >                   (match_operand:GPI 3 "register_operand" "r")))]
> >   ""
> >   "add\\t%<w>0, %<w>3, %<w>1, <shift> %2"
> >   [(set_attr "type" "alu_shift_imm")]
> > )
> >
> > It could not be distinguished by the type "alu_shift_imm" when writing
> "define_insn_reservation" for ADD (shifted register).
> > What should I do?
> 
> Just a guess - I'm not very familiar with the pipeline modeling, you probably
> need to expose two alternatives so you can assign a different type to the second
> one.
I'm considering such method, 
but if I do that I'm afraid it has side effects on other machine models of aarch64 series.
Some instructions' definition will be changed in aarch64.md file.

> Other than that modeling the more restrictive (or permissive?) variant might
> work good enough in practice.
Is your mean that an approximate modeling is good enough?

> a64fx is probably out-of-order anyway.
Yes, a64fx is an out-of-order architecture.

Regards
Qian

> 
> Richard.
> 
> > Regards
> > Qian
> >
> >
> >
>