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Subject: [MIPS] MADD issue
Date: Fri, 13 Apr 2007 00:26:00 -0000
Message-ID: <3CB54817FDF733459B230DD27C690CEC03EE8E3F@Exchange.mips.com>
From: "Fu, Chao-Ying" <fu@mips.com>
To: "Richard Sandiford" <richard@codesourcery.com>, <gcc@gcc.gnu.org>
Cc: "Thekkath, Radhika" <radhika@mips.com>, "Stephens, Nigel" <nigel@mips.com>
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Hi Richard,

  After tracing GCC 4.x to see why MADD is not generated for MIPS32,
I found out the main issue is that the pattern "adddi3"
is not available for MIPS32.  Because the missing
of adddi3, GCC 4.x needs to split 64-bit addition to 4 separate
RTL insns.  This leads to that the combining phase fails
to combine RTL insns to a single madd pattern.

  Could we enable "adddi3" for MIPS32 in GCC 4.x?  Or is there a=20
better way to generate MADD?  Thanks a lot!

Ex: (b67.c)
long long test (long long a, int b, int c)
{
  return a + (long long) b * (long long) c;
}

# gcc -S b67.c -O3 -mips32
(b67.s)
test:
        .frame  $sp,0,$31
        .mask   0x00000000,0
        .fmask  0x00000000,0
        .set    noreorder
        .set    nomacro

        mtlo    $5
        mthi    $4
        madd    $6,$7
        mflo    $3
        j       $31
        mfhi    $2

Regards,
Chao-ying
=20=20
---------------------------------------------------------------------
Ex: (mips.md in GCC 3.4)
(define_expand "adddi3"
  [(parallel [(set (match_operand:DI 0 "register_operand" "")
                   (plus:DI (match_operand:DI 1 "register_operand" "")
                            (match_operand:DI 2 "arith_operand" "")))
              (clobber (match_dup 3))])]
  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
{
....

(define_insn "adddi3_internal_1"
  [(set (match_operand:DI 0 "register_operand" "=3Dd,&d")
        (plus:DI (match_operand:DI 1 "register_operand" "0,d")
                 (match_operand:DI 2 "register_operand" "d,d")))
   (clobber (match_operand:SI 3 "register_operand" "=3Dd,d"))]
  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
{
  return (REGNO (operands[0]) =3D=3D REGNO (operands[1])
          && REGNO (operands[0]) =3D=3D REGNO (operands[2]))
    ? "srl\t%3,%L0,31\;sll\t%M0,%M0,1\;sll\t%L0,%L1,1\;addu\t%M0,%M0,%3"
    : "addu\t%L0,%L1,%L2\;sltu\t%3,%L0,%L2\;addu\t%M0,%M1,%M2\;addu\t%M0,%M=
0,%3";
}
  [(set_attr "type"     "darith")
   (set_attr "mode"     "DI")
   (set_attr "length"   "16")])

(define_insn "*smul_acc_di"
  [(set (match_operand:DI 0 "register_operand" "=3Dx")
        (plus:DI
         (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d=
"))
                  (sign_extend:DI (match_operand:SI 2 "register_operand" "d=
")))
         (match_operand:DI 3 "register_operand" "0")))]
  "(TARGET_MAD || ISA_HAS_MACC)
   && !TARGET_64BIT"
{
  if (TARGET_MAD)
    return "mad\t%1,%2";
  else if (TARGET_MIPS5500)
    return "madd\t%1,%2";
  else
    return "macc\t%.,%1,%2";
}
  [(set_attr "type"   "imadd")
   (set_attr "mode"   "SI")])
---------------------------------------------------------------------