From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12568 invoked by alias); 21 Oct 2002 13:59:09 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 12559 invoked from network); 21 Oct 2002 13:59:08 -0000 Received: from unknown (HELO scrabble.freeuk.net) (212.126.144.6) by sources.redhat.com with SMTP; 21 Oct 2002 13:59:08 -0000 Received: from [217.158.39.130] (helo=picochip.com) by scrabble.freeuk.net with esmtp (Exim 3.36 #2) id 183d5H-000Gnp-00 for gcc@gcc.gnu.org; Mon, 21 Oct 2002 14:59:07 +0100 Message-ID: <3DB40869.3080709@picochip.com> Date: Mon, 21 Oct 2002 09:06:00 -0000 From: Dan Towner Organization: picoChip Designs Ltd. User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.0.1) Gecko/20020823 Netscape/7.0 X-Accept-Language: en-gb, en-us, en MIME-Version: 1.0 To: gcc@gcc.gnu.org Subject: DFA Scheduling Queries Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2002-10/txt/msg01245.txt.bz2 Hi all, I am working on a port of gcc targeting a 16-bit VLIW DSP. I am using DFA instruction scheduling, and I have a couple of queries with regard to the best way of using this. The instructions can be divided into the basic classes: simpleAlu, complexAlu, loadStore, branch, and multiply. Each VLIW packet has 4 sub-packets, which can hold: 1) simpleAlu 2) simpleAlu or complexAlu 3) multiply or loadStore or branch 4) immediate constant I have created a cpu unit for each of these sub-packets: (define_query_cpu_unit "slot0,slot1,slot2,slotC") I have created reservations for each instruction type, so that it uses the correct slots. For example, a simple instruction can go in either slot 0 or slot 1: (define_insn_reservation "simpleAluInsn" 1 (and (eq_attr "type" "simpleAlu")) "(slot0|slot1)") Similarly for all the other instructions - they are mapped to the appropriate slots. My first question is how to represent the immediate constant slot. Currently, I have defined two forms for each instruction, one with the constant, and one without. For example, the above reservation could actually be: (define_insn_reservation "simpleAluInsn" 1 (and (eq_attr "type" "simpleAlu") (eq_attr "hasConstant" "false")) "(slot0|slot1)") (define_insn_reservation "simpleAluInsnWithConst" 1 (and (eq_attr "type" "simpleAlu") (eq_attr "hasConstant" "true")) "(slot0|slot1)+slotC") Thus, every one of my reservations comes in one of two forms: with and without a constant. Is this the best way of representing this requirement, or can I do better? My second question relates to scheduling instruction sequences which use status registers. For example, a 32-bit add can be handled as a 16-bit add (which generates a carry), followed by a 16-bit add-with-borrow (which pulls in and uses the previously generated carry flag). Once the first instruction has executed, the second instruction can execute in either slot0, or slot1, at any point, *provided no other instructions modifies the carry flag* (actually, to be precise, such modifying instructions can be executed in slot1, which can't modify the status flags). How can I describe such a situation using the DFA scheduler - is it even possible? Thanks, Dan. ============================================================================= Daniel Towner picoChip Designs Ltd., Riverside Buildings, 108, Walcot Street, BATH, BA1 5BG dant@picochip.com 07786 702589