* Re: machine description porting question.
[not found] <Pine.BSF.4.44.0210190225060.1915-100000@dair.pair.com>
@ 2002-10-22 14:58 ` Spundun Bhatt
2002-10-22 15:14 ` PLEASE DISREGARD MY PREVIOUR MAIL " Spundun Bhatt
2002-10-22 15:44 ` David Edelsohn
0 siblings, 2 replies; 3+ messages in thread
From: Spundun Bhatt @ 2002-10-22 14:58 UTC (permalink / raw)
To: Hans-Peter Nilsson; +Cc: gcc
Hi, I am redirecting my message from the gcc-bugs list to here.
I still have many confusions about creating temp registers in machine
description.
Hans-Peter Nilsson wrote:
>On Fri, 18 Oct 2002, Spundun Bhatt wrote:
>
>>Hi,
>>I am porting gcc to a new platform and it seems this mailing list is the
>>closest match. My apologies if this is not the correct place.
>>
>
>gcc@ is better.
>
>>The machine that I am porting to has an instruction set similar to IBM
>>rs6000, so we have taken rs6000 config files as the tmplate and are
>>trying to make modifications to it.
>>My question is mainly regarding adding a temporary register in any insn
>>definition in the machine description file.
>>
>
>It's not really "mainly", but a special case. (Getting a
>temporary register is done by other solutions in other
>contexts.)
>
I am still trying to get hold of -one- way to do this. :)
>
>>the scenario:
>>my machine doesnt have a compare instruction so I want to use subc
>>instruction (subtract and modify cc).
>>The compare instruction on powerpc looks similar to cmp RA,RB while
>>subtract instruction on my architecture looks like SUBC rD,rA,rB.
>>So gcc has to allocate a temporary register for rD, and I dont know how
>>to go about that.
>>
>
>You make the compare instruction pattern a define_expand which
>expands to the subtract insn. Or, since you say your machine is
>
I tried as you but couldnt get it working. Details follow.
>
>rs6000-like, you use the same expand-compare-insn-in-the-cc-user
>method used there, and expand to a *subtraction* (e.g.
>gen_subsi3) in your equivalent to rs6000_generate_compare. You
>get the temporary result register from gen_reg_rtx (mode).
>
I think this expand-compare.... is some mnemonic that you came up with
and I didnt understand, because I couldnt grep it in the cvs code :).
Here I need to clarify that the version of gcc that I am working with
is a branch from gcc 2.95.2 patched by motorola for the altivec
instruction set. In 2.95.2, the rs6000_generate_compare does not exist
so I couldnt try this sugession.
>
>brgds, H-P
>
>
the following is the snipped part of my original mail.
^ permalink raw reply [flat|nested] 3+ messages in thread
* PLEASE DISREGARD MY PREVIOUR MAIL Re: machine description porting question.
2002-10-22 14:58 ` machine description porting question Spundun Bhatt
@ 2002-10-22 15:14 ` Spundun Bhatt
2002-10-22 15:44 ` David Edelsohn
1 sibling, 0 replies; 3+ messages in thread
From: Spundun Bhatt @ 2002-10-22 15:14 UTC (permalink / raw)
To: Spundun Bhatt; +Cc: Hans-Peter Nilsson, gcc
hit the send button before completing the mail!! :( very sorry about that.
Spundun
Spundun Bhatt wrote:
> Hi, I am redirecting my message from the gcc-bugs list to here.
> I still have many confusions about creating temp registers in machine
> description.
>
> Hans-Peter Nilsson wrote:
>
>> On Fri, 18 Oct 2002, Spundun Bhatt wrote:
>>
>>> Hi,
>>> I am porting gcc to a new platform and it seems this mailing list is
>>> the
>>> closest match. My apologies if this is not the correct place.
>>>
>>
>> gcc@ is better.
>>
>>> The machine that I am porting to has an instruction set similar to IBM
>>> rs6000, so we have taken rs6000 config files as the tmplate and are
>>> trying to make modifications to it.
>>> My question is mainly regarding adding a temporary register in any insn
>>> definition in the machine description file.
>>>
>>
>> It's not really "mainly", but a special case. (Getting a
>> temporary register is done by other solutions in other
>> contexts.)
>>
> I am still trying to get hold of -one- way to do this. :)
>
>>
>>> the scenario:
>>> my machine doesnt have a compare instruction so I want to use subc
>>> instruction (subtract and modify cc).
>>> The compare instruction on powerpc looks similar to cmp RA,RB while
>>> subtract instruction on my architecture looks like SUBC rD,rA,rB.
>>> So gcc has to allocate a temporary register for rD, and I dont know how
>>> to go about that.
>>>
>>
>> You make the compare instruction pattern a define_expand which
>> expands to the subtract insn. Or, since you say your machine is
>>
> I tried as you but couldnt get it working. Details follow.
>
>>
>> rs6000-like, you use the same expand-compare-insn-in-the-cc-user
>> method used there, and expand to a *subtraction* (e.g.
>> gen_subsi3) in your equivalent to rs6000_generate_compare. You
>> get the temporary result register from gen_reg_rtx (mode).
>>
> I think this expand-compare.... is some mnemonic that you came up with
> and I didnt understand, because I couldnt grep it in the cvs code :).
> Here I need to clarify that the version of gcc that I am working with
> is a branch from gcc 2.95.2 patched by motorola for the altivec
> instruction set. In 2.95.2, the rs6000_generate_compare does not exist
> so I couldnt try this sugession.
>
>>
>> brgds, H-P
>>
>>
> the following is the snipped part of my original mail.
>
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: machine description porting question.
2002-10-22 14:58 ` machine description porting question Spundun Bhatt
2002-10-22 15:14 ` PLEASE DISREGARD MY PREVIOUR MAIL " Spundun Bhatt
@ 2002-10-22 15:44 ` David Edelsohn
1 sibling, 0 replies; 3+ messages in thread
From: David Edelsohn @ 2002-10-22 15:44 UTC (permalink / raw)
To: Spundun Bhatt; +Cc: Hans-Peter Nilsson, gcc
I would suggest that you base your port to the new processor on a
more recent version of GCC than gcc-2.95.
If you need to create a temporary register, use a define_expand
pattern which contains gen_reg_rtx (MODE), where "MODE" is whatever mode
register you need, in your case, matching the mode of the other arguments
to the subtract. For instance, look at the extendqisi2_no_power pattern
which implements a sign-extend as two arithmetic shifts to propagate the
sign bit.
David
^ permalink raw reply [flat|nested] 3+ messages in thread
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2002-10-22 14:58 ` machine description porting question Spundun Bhatt
2002-10-22 15:14 ` PLEASE DISREGARD MY PREVIOUR MAIL " Spundun Bhatt
2002-10-22 15:44 ` David Edelsohn
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