* latency in define_insn_reservation
@ 2003-12-09 6:06 ml
2003-12-10 7:55 ` Jim Wilson
0 siblings, 1 reply; 2+ messages in thread
From: ml @ 2003-12-09 6:06 UTC (permalink / raw)
To: gcc
In the DFA pipeline description, is the latency time equal to the number of cycles between instruction issue and instruction results or is it number of cycles btw instr issue and intruction results + 1 (the instr issue cycle also being counted) ?
If instr I is issued cycle = t and the results are usable in cylce t+1, should the latency in define_insn_reservation be 1 or 0?
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: latency in define_insn_reservation
2003-12-09 6:06 latency in define_insn_reservation ml
@ 2003-12-10 7:55 ` Jim Wilson
0 siblings, 0 replies; 2+ messages in thread
From: Jim Wilson @ 2003-12-10 7:55 UTC (permalink / raw)
To: ml; +Cc: gcc
ml@bitbash.net wrote:
> If instr I is issued cycle = t and the results are usable in cylce t+1, should the latency in define_insn_reservation be 1 or 0?
The latency should be 1. Try looking at existing dfa scheduler
descriptions. I doubt that you will find any that use a latency of
zero, but there are lots that use a latency of 1 for simple instructions
that you would expect to have single cycle latency.
--
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com
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