From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 21827 invoked by alias); 15 Aug 2019 18:23:49 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 21818 invoked by uid 89); 15 Aug 2019 18:23:48 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-4.4 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Aug 2019 18:23:47 +0000 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 221A9315C015 for ; Thu, 15 Aug 2019 18:23:46 +0000 (UTC) Received: from tobol.usersys.redhat.com (unused-10-15-17-174.yyz.redhat.com [10.15.17.174]) by smtp.corp.redhat.com (Postfix) with ESMTP id E64D243FD5 for ; Thu, 15 Aug 2019 18:23:45 +0000 (UTC) Subject: Re: Indirect memory addresses vs. lra To: gcc@gcc.gnu.org References: <2B3A4EAB-D69E-4714-8FC4-C25E36B07BFF@comcast.net> <20190808172102.GH31406@gate.crashing.org> <2EEBCFAE-FF25-4664-AA5F-B3299CEA3CB1@comcast.net> <20190808191914.GK31406@gate.crashing.org> <20190809081439.baoyu3ii5i2qfbzt@jocasta.intra> <70b9bcc9-e12a-78b4-b8cc-a67b7ca3d38d@redhat.com> <20190810060553.m6e42sovw7s4xqoa@jocasta.intra> <20190815173559.kbp3uja7jklx74iy@jocasta.intra> From: Vladimir Makarov Message-ID: <3c6c87ce-a38f-728d-e083-aa066d531790@redhat.com> Date: Thu, 15 Aug 2019 18:23:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190815173559.kbp3uja7jklx74iy@jocasta.intra> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2019-08/txt/msg00113.txt.bz2 On 8/15/19 1:35 PM, John Darrington wrote: > On Thu, Aug 15, 2019 at 12:29:13PM -0400, Vladimir Makarov wrote: > > > Thank you for providing the sources.?? It helped me to understand what is > going on.?? So the test crashes on > > /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c: In function ???f1???: > /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1: error: unable to find a register to spill > /home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c:10:1: error: this is the insn: > (insn 14 49 15 2 (set (mem:SI (plus:PSI (reg/f:PSI 40 [34]) > (const_int 32 [0x20])) [2 S4 A64]) > (mem:SI (reg:PSI 41) [2 *p_5(D)+0 S4 A8])) "/home/jmd/Source/GCC2/gcc/testsuite/gcc.c-torture/compile/pr53410-2.c":9:9 95 {*movsi} > (expr_list:REG_DEAD (reg:PSI 41) > (expr_list:REG_DEAD (reg/f:PSI 40 [34]) > (nil)))) > > Thanks for taking a look. > > Your target has only 2 non-fixed addr registers (r8, r9). One (r9) is defined as a hard reg pointer pointer. > > That is correct. > > Honestly, I never saw a target with such register constraints. > > My recollection is that MC68HC11 was the same. > > So what can be done, imho. The simplest solution would be preventing insns with more one memory operand. > > I tried this solution earlier. But unfortunately it makes things worse. What happens is it libgcc cannot > even be built -- ICEs occur on a memory from address reg insn such as: > > (insn 117 2981 3697 5 (set (mem/f:PSI (plus:PSI (reg:PSI 1309) > (const_int 102 [0x66])) [3 fs_129(D)->pc+0 S4 A8]) > (reg:PSI 1310)) "/home/jmd/Source/GCC2/libgcc/unwind-dw2.c":977:9 96 {movpsi} > I see.  Then for the insn, you could try to create a pattern "memory,special memory constraint".  The special memory constraint should satisfy only spilled pseudo (pseudo with reg_renumber == -1).  I believe lra-constraints.c can spill the pseudo and the end you will have mem[disp1 + r8|r9|sp] = mem[disp1+sp]. It might work.  If it is not, we could modify LRA to do this. Another solution would be adding unexisting register Z and for mem:psi [psi:r] = Z you could emit an assembler insn : mem[psi:r] = a stack slot corresponding Z.