question about scheduling optimization in machine description

question about scheduling optimization in machine description

[Spundun Bhatt]

Hi all..

I have a couple of problems with my target which I have been ffighting 
with for a few months now, so I have decided to try here. In this email 
I am writing about on of them. It will be great if someone can suggest a 
way out of it.. if not.. a pointer to a simlar implementation in any of 
the existing target would be great.

On my architecture, floating point instructions run faster when put 
backto back with no integer or load/store instructions in the middle.  
So I want to ask the compiler to group as many such instructions 
togather as possible. The reason is that FP unit is pipelined and it 
stalls all instructions except other floating point instructions until 
the float pipeline is clear. (to save on WB hazard detection). 

I have thought about this a lot but ccant find a solution that will be 
helpful... any ideas? or has it been done for some target for certain 
instructions?

Thanx
Spundun

-- 
If popularity breeds vulnerability, Apache should have far more vulnerabilities than IIS. It doesn't.

Re: question about scheduling optimization in machine description

[Richard Henderson]

On Thu, Sep 09, 2004 at 05:38:17PM -0700, Spundun Bhatt wrote:
> On my architecture, floating point instructions run faster when put 
> backto back with no integer or load/store instructions in the middle.  
> So I want to ask the compiler to group as many such instructions 
> togather as possible. The reason is that FP unit is pipelined and it 
> stalls all instructions except other floating point instructions until 
> the float pipeline is clear. (to save on WB hazard detection). 
> 
> I have thought about this a lot but ccant find a solution that will be 
> helpful... any ideas?

You may be able to do clever things with the scheduling DFA.
We do instruction bundling for pentiumpro this way, for instance.

Also examine the TARGET_SCHED_REORDER target hook.  That'll
let you choose from the ready instructions to fill just 
about any packing scheme you need.  You'll have to track
the instruction state yourself in that case; there are other
hooks to enable that.



r~

Re: question about scheduling optimization in machine description

[Paolo Bonzini]

> On my architecture, floating point instructions run faster when put 
> backto back with no integer or load/store instructions in the middle.  
> So I want to ask the compiler to group as many such instructions 
> togather as possible. The reason is that FP unit is pipelined and it 
> stalls all instructions except other floating point instructions until 
> the float pipeline is clear. (to save on WB hazard detection).

You should already have (in your scheduling description) a unit for each 
fp pipeline stage, e.g. fp1, fp2, fp3, fp4, fp5.

FP instructions have normal reservations, something like 
fp1,fp2,fp3,fp4,fp5 for example.

Other instructions, in addition to what they really reserve, keep all of 
the FP units busy on their first cycle, like (alu+fp1+fp2+fp3+fp4+fp5).
                                                  ^^^^^^^^^^^^^^^^^^^^

I'm not sure it works, but "on paper" it looks like it should.

For a very simple close-to-trivial scheduling description, see the ARC 
port.  Another possibility can be the frv.md file, or sh4.md file in 
config/sh.

Paolo

Re: question about scheduling optimization in machine description

[Spundun Bhatt]

Richard Henderson wrote:

>On Thu, Sep 09, 2004 at 05:38:17PM -0700, Spundun Bhatt wrote:
>  
>
>>On my architecture, floating point instructions run faster when put 
>>backto back with no integer or load/store instructions in the middle.  
>>So I want to ask the compiler to group as many such instructions 
>>togather as possible. The reason is that FP unit is pipelined and it 
>>stalls all instructions except other floating point instructions until 
>>the float pipeline is clear. (to save on WB hazard detection). 
>>
>>I have thought about this a lot but ccant find a solution that will be 
>>helpful... any ideas?
>>    
>>
>
>You may be able to do clever things with the scheduling DFA.
>We do instruction bundling for pentiumpro this way, for instance.
>  
>
Thanks to you a Paolo for the reply.

Unfortunately I omitted an important detail in my problem. The fact that
I am working on a gcc derived from 2.95.3 :((. I studied the new and old
internals book... and came to conclusion that both your replies refer to
the new scheduling method that is not available in 2.95.3. Sorry for not
mentioning this before. Is there anyway to do this in the 2.95.3 scheduler?

Thank you
Spundun
btw.  I am considering just putting the old target directory in the new
gcc 3.4 's config directory .... do you think that can work? (within a
day or a week?)

>Also examine the TARGET_SCHED_REORDER target hook.  That'll
>let you choose from the ready instructions to fill just 
>about any packing scheme you need.  You'll have to track
>the instruction state yourself in that case; there are other
>hooks to enable that.
>
>
>
>r~
>
>  
>


-- 
If popularity breeds vulnerability, Apache should have far more 
vulnerabilities than IIS. It doesn't.

Re: question about scheduling optimization in machine description

[Richard Henderson]

On Sat, Sep 11, 2004 at 10:00:51AM -0700, Spundun Bhatt wrote:
> Is there anyway to do this in the 2.95.3 scheduler?

Probably not.

> btw.  I am considering just putting the old target directory in the new
> gcc 3.4 's config directory .... do you think that can work? (within a
> day or a week?)

Within a week, perhaps.


r~