From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32608 invoked by alias); 24 Nov 2005 20:51:42 -0000 Received: (qmail 32600 invoked by uid 22791); 24 Nov 2005 20:51:41 -0000 X-Spam-Check-By: sourceware.org Received: from lon-del-04.spheriq.net (HELO lon-del-04.spheriq.net) (195.46.50.101) by sourceware.org (qpsmtpd/0.31) with ESMTP; Thu, 24 Nov 2005 20:51:40 +0000 Received: from lon-out-03.spheriq.net ([195.46.50.131]) by lon-del-04.spheriq.net with ESMTP id jAOKpbvI016220 for ; Thu, 24 Nov 2005 20:51:37 GMT Received: from lon-cus-02.spheriq.net (lon-cus-02.spheriq.net [195.46.50.38]) by lon-out-03.spheriq.net with ESMTP id jAOKpasj010523 for ; Thu, 24 Nov 2005 20:51:36 GMT Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by lon-cus-02.spheriq.net with ESMTP id jAOKpZj4025888 (version=TLSv1/SSLv3 cipher=EDH-RSA-DES-CBC3-SHA bits=168 verify=OK); Thu, 24 Nov 2005 20:51:35 GMT Received: from zeta.dmz-eu.st.com (ns2.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 14EF1DA41; Thu, 24 Nov 2005 20:51:34 +0000 (GMT) Received: by zeta.dmz-eu.st.com (STMicroelectronics, from userid 60012) id 52374474BA; Thu, 24 Nov 2005 20:54:36 +0000 (GMT) Received: from zeta.dmz-eu.st.com (localhost [127.0.0.1]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 13E2175995; Thu, 24 Nov 2005 20:54:36 +0000 (UTC) Received: from mail1.bri.st.com (mail1.bri.st.com [164.129.8.218]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8CA11474B1; Thu, 24 Nov 2005 20:54:35 +0000 (GMT) Received: from st.com (linsvr9.bri.st.com [164.129.13.87]) by mail1.bri.st.com (MOS 3.5.8-GR) with ESMTP id CGZ97485 (AUTH "joern rennecke"); Thu, 24 Nov 2005 20:51:31 GMT Message-ID: <438627D3.1050209@st.com> Date: Thu, 24 Nov 2005 20:51:00 -0000 From: Joern RENNECKE User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.6) Gecko/20040113 MIME-Version: 1.0 To: Ian Lance Taylor , Andrew MacLeod Cc: gcc mailing list Subject: Re: Register Allocation Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit X-O-Spoofed: Not Scanned X-O-General-Status: No X-O-Spam1-Status: Not Scanned X-O-Spam2-Status: Not Scanned X-O-URL-Status: Not Scanned X-O-Virus1-Status: No X-O-Virus2-Status: Not Scanned X-O-Virus3-Status: No X-O-Virus4-Status: No X-O-Virus5-Status: Not Scanned X-O-Image-Status: Not Scanned X-O-Attach-Status: Not Scanned X-SpheriQ-Ver: 4.2.0 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2005-11/txt/msg01204.txt.bz2 In http://gcc.gnu.org/ml/gcc/2005-11/msg01163.html, Ian Lance Taylor wrote: > Either way, register elimination can cause addresses which were valid > to become invalid, typically because valid offsets from the frame > pointer become invalid offsets from the stack pointer. So that needs > to be cleaned up somewhere. This is not just about some requiring some cleanup somewhere. Register elimination and stack slot allocation determine the exact addresses that are used, which in turn determine what reload inheritance is possible for address reloads that are for stack slots which are close together on the stack. Getting this right is essential to avoid performance degradation on some platforms. These targets typically use LEGITIMIZE_RELOAD_ADDRESS to split out-of-range addresses into a normal form with a base address load and a memory access using this base with a small offset. On the other hand, the hard register spills appear to offer a new opportunity: we have talked about shrink-wrapping code in the past, but have never implemented this in gcc. I think that register saves/restores can be considered special cases of hard register spills. In order to do this efficiently, there would have to be some interface with the target to exploit insn sequences that can save/restore multiple registers more efficiently in bulk, .e.g load/store multiple, or auto-increment use on targets that are otherwise ACCUMULATE_OUTGOING_ARGS. On the other hand, these techniques can also help when we need to spill multiple hard registers around a tight loop.