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From: Sylvain Munaut <tnt@246tNt.com>
To: Hans-Peter Nilsson <hp@bitrange.com>, gcc@gcc.gnu.org
Subject: Re: Design a microcontroller for gcc
Date: Thu, 16 Feb 2006 00:26:00 -0000	[thread overview]
Message-ID: <43F3C6F8.7080007@246tNt.com> (raw)
In-Reply-To: <Pine.BSF.4.58.0602151657550.72020@dair.pair.com>

Hans-Peter Nilsson wrote:
> On Wed, 15 Feb 2006, Sylvain Munaut wrote:
> 
>>	* 2 flags Carry & Zero for testing.
> 
> 
> I think most of your questions have been answered, so let me
> just add that if nothing else, the port will be much simplified
> if you make sure that only specific compare instructions set
> condition codes, i.e. not as a nice side-effect of move, add and
> sub - or at least make such condition-code side-effects
> optional.  It depends on too many undisclosed details like
> pipeline restrictions to say whether performance is generally
> better or worse, but I can tell for sure that the GCC port will
> be simpler with a specific set of condition-code setting insns.

Making it optionnal is not hard nor expensive in hardware, the problem
is that my opcodes need to be 18 bits and I won't have space to stuff
another option bit ...

What I was thinking for the moment was to have :
 - sign is always the msb of the last ALU output
 - add/sub to modify all flags
 - move/xor/and/not/or only affect zero (and sign)
 - shift operations always affect carry and zero
 - Have some specific instructions like compare and test, but theses
   would only operate on registers (and not on immediate)

What's so bad about have the flag as side-effects ?

Here it's a simple MCU, it doesn't have a very long pipeline and that
pipeline is 'almost' invisible to the end-user exception for memory
fetch and io/access ...


> BTW, it depends on the compare (and branch) instructions whether
> just two flags are sufficient.
g
Adding Sign and overflow is pretty easy. And the compare
instruction/logic path shouldn't be a problem either.

MIPS has no flag ??? how does branching work ?



Finally, about immediates, I'm thinking of having instruction like add
could have 4 different forms :
add rD, rA, rB
add rA, rA, imm
add rA, rA, imm<<8
add rA, rA, signextend(imm)

Is that kind of manipulation on the immediate well understood by gcc
internals ?

Or maybe just allow immediates in the mov but that seems like a big
penalty ...


Sylvain

  parent reply	other threads:[~2006-02-16  0:26 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-02-14 23:22 Sylvain Munaut
2006-02-14 23:40 ` DJ Delorie
2006-02-15  0:28   ` Sylvain Munaut
2006-02-15  0:41     ` DJ Delorie
2006-02-15 19:59       ` Sylvain Munaut
2006-02-15 20:06         ` DJ Delorie
2006-02-15 20:23           ` Paul Brook
2006-02-15 21:21             ` DJ Delorie
2006-02-15 22:10 ` Hans-Peter Nilsson
2006-02-15 23:10   ` David Daney
2006-02-16  0:26   ` Sylvain Munaut [this message]
2006-02-16  0:46     ` DJ Delorie
2006-02-16  2:49     ` Hans-Peter Nilsson
2006-02-16  3:21       ` DJ Delorie
2006-02-16  3:34         ` Hans-Peter Nilsson
2006-02-16  3:37           ` Hans-Peter Nilsson
2006-02-16  3:44             ` DJ Delorie
2006-02-16  3:40           ` DJ Delorie
2006-02-16  3:56             ` Hans-Peter Nilsson
2006-02-16  4:10               ` Hans-Peter Nilsson
2006-02-16  4:17                 ` DJ Delorie
2006-02-16  4:13               ` DJ Delorie
2006-02-16 11:42         ` Hans-Peter Nilsson
2006-02-16 20:49           ` Sylvain Munaut
2006-02-17  0:28             ` Hans-Peter Nilsson
2006-02-20  8:54               ` Sylvain Munaut

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