From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12452 invoked by alias); 25 Oct 2019 11:07:50 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 12444 invoked by uid 89); 25 Oct 2019 11:07:50 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-4.3 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS autolearn=ham version=3.3.1 spammy=cheaper, gcc10, H*r:present, H*r:did X-HELO: mo4-p00-ob.smtp.rzone.de Received: from mo4-p00-ob.smtp.rzone.de (HELO mo4-p00-ob.smtp.rzone.de) (85.215.255.23) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 Oct 2019 11:07:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1572001665; s=strato-dkim-0002; d=gjlay.de; h=Date:Message-ID:Subject:From:To:X-RZG-CLASS-ID:X-RZG-AUTH:From: Subject:Sender; bh=uPZAmevHnYhi0xUA0uvkrB62992k/b5S0ebDo5UbZ2I=; b=BI7Wbw0WUBWkBEKNCIvjQfTLHo1KSmK60b4FcyhRTNHyLik6xx3URIUtRpFNeYQmxH aTgb4lPWhO7+dYnfXe5iZoLSxKJzECSSI15BEN+RTztalmc2irI3VBeh3VKcjqWrBim3 l5ou/ATqQ3UG3o8U4wUHjlR4SHsJRiTP6Ic3q/j5cdndzAHM5dH/WdHtZ0LTr9elObHw 44uPwu1U6XRUG/PkAoPGRqhnGA3Yod5O+bRUjaYbmLhYuBvay3IdrTSMRCqPqVSBTdOY EDCB+uvTkErNUFzs7BW0yefDJfwH8loBqcCaDZ9Q8g5EwuxoOjx+xs/bunRPdxmOkR8w AqtA== Received: from [192.168.22.245] by smtp.strato.de (RZmta 44.28.1 AUTH) with ESMTPSA id t01740v9PB7jTZn (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate) for ; Fri, 25 Oct 2019 13:07:45 +0200 (CEST) To: gcc@gcc.gnu.org From: Georg-Johann Lay Subject: Code bloat due to silly IRA cost model? Message-ID: <47b10439-21b8-81f6-3838-a2bcd0fa8048@gjlay.de> Date: Fri, 25 Oct 2019 11:07:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2019-10/txt/msg00156.txt.bz2 Hi, I am trying to track down a code bloat issue and am stuck becauce I do not understand IRA's cose model. The test case is as simple as it gets: float func (float); float call (float f) { return func (f); } IRA dump shows the following insns: (insn 14 4 2 2 (set (reg:SF 44) (reg:SF 22 r22 [ f ])) "bloat.c":4:1 85 {*movsf} (expr_list:REG_DEAD (reg:SF 22 r22 [ f ]) (nil))) (insn 2 14 3 2 (set (reg/v:SF 43 [ f ]) (reg:SF 44)) "bloat.c":4:1 85 {*movsf} (expr_list:REG_DEAD (reg:SF 44) (nil))) (note 3 2 6 2 NOTE_INSN_FUNCTION_BEG) (insn 6 3 7 2 (set (reg:SF 22 r22) (reg/v:SF 43 [ f ])) "bloat.c":5:12 85 {*movsf} (expr_list:REG_DEAD (reg/v:SF 43 [ f ]) (nil))) (call_insn/j 7 6 8 2 (parallel [ #14 sets pseudo 44 from arg register R22. #2 moves it to pseudo 43 #6 moves it to R22 as it prepares for call_insn #7. There are 2 allocnos and cost: Pass 0 for finding pseudo/allocno costs a1 (r44,l0) best NO_REGS, allocno NO_REGS a0 (r43,l0) best NO_REGS, allocno NO_REGS a0(r43,l0) costs: ADDW_REGS:32000 SIMPLE_LD_REGS:32000 LD_REGS:32000 NO_LD_REGS:32000 GENERAL_REGS:32000 MEM:9000 a1(r44,l0) costs: ADDW_REGS:32000 SIMPLE_LD_REGS:32000 LD_REGS:32000 NO_LD_REGS:32000 GENERAL_REGS:32000 MEM:9000 which is quite odd because MEM is way more expensive here than any REG. Okay, so let's boost the MEM cost (TARGET_MEMORY_MOVE_COST) by a factor of 100: a1 (r44,l0) best NO_REGS, allocno NO_REGS a0 (r43,l0) best NO_REGS, allocno NO_REGS a0(r43,l0) costs: ADDW_REGS:3200000 SIMPLE_LD_REGS:3200000 LD_REGS:3200000 NO_LD_REGS:3200000 GENERAL_REGS:3200000 MEM:801000 a1(r44,l0) costs: ADDW_REGS:3200000 SIMPLE_LD_REGS:3200000 LD_REGS:3200000 NO_LD_REGS:3200000 GENERAL_REGS:3200000 MEM:801000 What??? The REG costs are 100 times higher, and stille higher that the MEM costs. What the heck is going on? Setting TARGET_REGISTER_MOVE_COST and also TARGET_MEMORY_MOVE_COST to 0 yiels: a0(r43,l0) costs: ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 MEM:0 a1(r44,l0) costs: ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 GENERAL_REGS:0 MEM:0 as expected, i.e. there is no other hidden source of costs considered by IRA. And even TARGET_REGISTER_MOVE_COST = 0 and TARGET_MEMORY_MOVE_COST = original gives: a0(r43,l0) costs: ADDW_REGS:32000 SIMPLE_LD_REGS:32000 LD_REGS:32000 NO_LD_REGS:32000 GENERAL_REGS:32000 MEM:9000 a1(r44,l0) costs: ADDW_REGS:32000 SIMPLE_LD_REGS:32000 LD_REGS:32000 NO_LD_REGS:32000 GENERAL_REGS:32000 MEM:9000 How the heck do I tell ira-costs that registers are way cheaper than MEM? Johann p.s. test case compiled with $ avr-gcc bloat.c -S -Os -dp -da -fsplit-wide-types-early -v Target: avr Configured with: ../../gcc.gnu.org/trunk/configure --target=avr --prefix=/local/gnu/install/gcc-10 --disable-shared --disable-nls --with-dwarf2 --enable-target-optspace=yes --with-gnu-as --with-gnu-ld --enable-checking=release --enable-languages=c,c++ --disable-gcov Thread model: single Supported LTO compression algorithms: zlib gcc version 10.0.0 20191021 (experimental) (GCC)