From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4615 invoked by alias); 17 Mar 2010 14:10:27 -0000 Received: (qmail 4598 invoked by uid 22791); 17 Mar 2010 14:10:26 -0000 X-SWARE-Spam-Status: No, hits=-2.6 required=5.0 tests=BAYES_00 X-Spam-Check-By: sourceware.org Received: from mailgate.blueteddy.net (HELO mailgate.blueteddy.net) (80.176.108.50) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 17 Mar 2010 14:10:21 +0000 Received: from [192.168.0.189] (adsl-99-74-119-22.dsl.pltn13.sbcglobal.net [99.74.119.22]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mailgate.blueteddy.net (Postfix) with ESMTPSA id B8D121746B89; Wed, 17 Mar 2010 14:10:16 +0000 (GMT) Subject: Re: Is it possible to port GCC backend to a architecture with very limited hard registers? Mime-Version: 1.0 (Apple Message framework v1077) Content-Type: text/plain; charset=us-ascii From: Dave Hudson In-Reply-To: <11825351.1268834467283.JavaMail.root@elwamui-muscovy.atl.sa.earthlink.net> Date: Wed, 17 Mar 2010 15:01:00 -0000 Cc: redriver jiang , gcc@gcc.gnu.org Content-Transfer-Encoding: quoted-printable Message-Id: <4AA7B76E-7E05-40C4-BE94-9FDD42DA346A@blueteddy.net> References: <11825351.1268834467283.JavaMail.root@elwamui-muscovy.atl.sa.earthlink.net> To: Alan Lehotsky X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2010-03/txt/msg00220.txt.bz2 We only had one real 8-bit accumulator on that port (the W register) which = we did not expose the RA, instead exposing 32 "virtual" 8-bit registers fro= m which we could construct 8, 16, 32 and 64-bit pairs. The key to really g= ood code generation was to aggresively split the larger pseudo-operations a= fter reload and eliminate all possible redundancy. The IP2k did have 2 offsettable address pointers though, one as a stack poi= nter and one as a data pointer which made the code much easier to manage (t= here was also one that wasn't offsettable and wasn't anywhere near as usefu= l). I can imagine that any code where there's only one address register is= going to be very messy because it will be permenantly swapping things in = and out of it as things like register spills happen. Cheers, Dave On 17 Mar 2010, at 14:01, Alan Lehotsky wrote: > Almost certainly you will run into severe problems in the reload phase. >=20 > You might also profitably study the ip2k port. This is a ALU machine, bu= t it does have multiple > address registers. >=20 >=20 > -----Original Message----- >> From: redriver jiang >> Sent: Mar 17, 2010 8:55 AM >> To: gcc@gcc.gnu.org >> Subject: Is it possible to port GCC backend to a architecture with very = limited hard registers? >>=20 >> Hi all, >>=20 >> Right now I attempts to port the GCC backend to a MCU with very >> limited hard registers: only one 8 bit ACC reg, one 16 bit base reg >> for addressing, one stats reg. >> I searched the GCC backend porting, and seems 68HC1X has the similar >> scene, but it use many "ram simulated" register. I wonder that if it >> is possbile to provided thislimited 3 register to GCC bankend, and let >> all 16bit(HImode), 32bit(SImode) operands spilled to stack. >>=20 >> Thanks! >>=20 >> Redriver >=20