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Date: Tue, 06 Oct 2009 03:10:00 -0000
From: Richard Henderson <rth@redhat.com>
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To: Mohamed Shafi <shafitvm@gmail.com>
CC: GCC <gcc@gcc.gnu.org>
Subject: Re: How to split 40bit data types load/store?
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On 10/05/2009 07:02 AM, Mohamed Shafi wrote:
> . But now it seems that i
> need to split the pattern before reload also.

Oh?  Why?

> The only addressing mode
> supported for accessing this section is (SP+offset).

Ouch.  Is there no general register to high-8bit move either?
So you can't do

   load (R0), D0
   load (R0+4), R1
   move.ext R1, D0.u8

> (define_expand "movda"
>   [(set (match_operand:DA 0 "nonimmediate_operand" "")
>         (match_operand:DA 1 "nonimmediate_operand" ""))]

So, DAmode is your 40-bit value.  What's SAmode?

> (define_insn "load_reg_ext"
>   [(set (subreg:SA (zero_extract:DA (match_operand:DA 0 "register_operand" "=d")
>                          (const_int 8)
>                          (const_int 24)) 4)
>         (match_operand:SA 1 "memory_operand" "Sd3"))]

This pattern doesn't look kosher with the subreg outside the 
zero_extract.  I know I mentioned using zero_extract in an earlier 
message, but that may not actually work with an object larger than word 
size.  You may be better off with an unspec:

   (set (match_operand:DA 0 "register_operand" "=d")
        (unspec:DA [(match_operand:DA 1 "register_operand" "0")
		   (match_operand:SA 2 "memory_operand" "Sd3")]
		  UNSPEC_LOAD_REG_EXT))

or whatever you actually need.


r~