* 32 Bit Backend with 3 Registers
@ 2010-05-10 11:56 Eggenmüller Bernd
0 siblings, 0 replies; only message in thread
From: Eggenmüller Bernd @ 2010-05-10 11:56 UTC (permalink / raw)
To: gcc
Hi,
I have a problem to compile the libgcc2 with a new gcc backend.
I have a little processor with 4 registers A X Y and R0(0) with 32 Bit.
R0(0) is the stackpointer and Y is the basepointer.
So i only have the registers A and X to calculate.
It always gave me an error that there are to less spill registers,
when trying to compile the the _mulvsi3 function of the libgcc2.
So I tried to add more registers, which are R1(0), R2(0), R3(0), R4(0)
and R5(0) with 32 Bit length.
The problem is that this registers cant calculate anything they are only
to hold values.
They can be written as example with mov R1(0), A and read with mov A, R1(0).
I implemented an new register class for this R.. registers and added the
mov instruvtion to the movsi
pattern. And now I get an error at the negdi2 function of the libgcc2,
this means it doesn't compile as
far as the first version with less registers.
Regards
Egge-B
Here is the Error massage and the .h and .md file
-4.4.1/build/./gcc/ -B/home/user/test/local/hicovec/bin/
-B/home/user/test/local/hicovec/lib/ -isystem
/home/user/test/local/hicovec/include -isystem
/home/user/test/local/hicovec/sys-include -g -O2 -O2 -g -O2 -DIN_GCC
-DCROSS_DIRECTORY_STRUCTURE -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wcast-qual
-Wold-style-definition -isystem ./include -g -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -Dinhibit_libc -I. -I. -I../.././gcc
-I../.././../libgcc -I../.././../libgcc/. -I../.././../libgcc/../gcc
-I../.././../libgcc/../include -DHAVE_CC_TLS -o _negdi2.o -MT _negdi2.o
-MD -MP -MF _negdi2.dep -DL_negdi2 -c ../.././../libgcc/../gcc/libgcc2.c \
cc1: Warnung: Zielsystem unterstÃŒtzt keine Testausgaben
cc1: Warnung: Zielsystem unterstÃŒtzt keine Testausgaben
cc1: Warnung: Zielsystem unterstÃŒtzt keine Testausgaben
../.././../libgcc/../gcc/libgcc2.c: In Function »__negdi2«:
../.././../libgcc/../gcc/libgcc2.c:76: intern Compiler-Error: in
refers_to_regno_for_reload_p, at reload.c:6440
//bein .md file
***********************************************************************************************************************
;; from avr
(define_attr "cc" "none,set_cz,set_z,compare,clobber"
(const_string "clobber")) ;clobber by default
(define_constants
[(A_REGNUM 0)
(X_REGNUM 1)
(BP_REGNUM 2)
(SP_REGNUM 3)
]
)
(define_mode_iterator SIF [SI SF])
;;(define_predicate "register_axy_or_0"
;; (ior
;; (match_operand 0 "register_operand")
;; (and (match_code "const_int")
;; (match_test "op == const0_rtx"))))
;defines the Register Class for Register A
(define_predicate "register_a"
(match_operand 0 "register_operand")
{
unsigned int regno;
regno = REGNO(op);
return regno == 0;
})
;;EGGE
;;defines the Register Class for ARITH_REGS (AXY)
(define_predicate "register_axy"
(match_operand 0 "register_operand")
{
unsigned int regno;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
regno = REGNO (op);
//printf("%d\t",regno);
return true;
return (regno >= FIRST_PSEUDO_REGISTER || (regno>=0 && regno<=3));
})
(define_predicate "register_axy0"
(ior (match_operand 0 "register_axy")
(and (match_code "const_int")
(match_test "op == const0_rtx"))))
(define_predicate "nonmemory_axyi"
(ior (match_operand 0 "register_axy")
(match_operand 0 "immediate_operand")))
;;Egge end
; ARITH Operations
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_axy" "=a")
(plus:SI
(match_operand:SI 1 "register_axy0" "a0")
(match_operand:SI 2 "nonmemory_axyi" "ai")))]
""
"add %0, %1, %2 ; %0 = %1 + %2"
[(set_attr "cc" "set_cz")])
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_axy" "=a")
(minus:SI
(match_operand:SI 1 "register_axy0" "a")
(match_operand:SI 2 "nonmemory_axyi" "ai")))
]
""
"sub %0, %1, %2 ; %0 = %1 - %2"
[(set_attr "cc" "set_cz")])
(define_insn "negsi2"
[(set (match_operand:SI 0 "register_axy" "=a")
(neg:SI (match_operand:SI 1 "nonmemory_axyi" "ai")))]
""
"sub %0, 0, %1 ; %0 = -%1"
[(set_attr "cc" "set_cz")])
(define_insn "cmpsi"
[(set (cc0)
(compare
(match_operand:SI 0 "register_axy" "a")
(match_operand:SI 1 "nonmemory_axyi" "ai")))]
""
"sub 0, %0, %1 ; %0 < %1?"
[(set_attr "cc" "compare")])
(define_insn "tstsi"
[(set (cc0)
(match_operand:SI 0 "register_axy" "a"))]
""
"sub 0, %0, 0 ; %0 != 0?"
[(set_attr "cc" "compare")])
(define_insn "*rev_tstsi"
[(set (cc0)
(compare (const_int 0)
(match_operand:SI 0 "register_axy" "a")))]
""
"sub 0, 0, %0 ; 0 != %0?"
[(set_attr "cc" "compare")])
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_axy" "=a")
(and:SI
(match_operand:SI 1 "register_axy0" "a0")
(match_operand:SI 2 "nonmemory_axyi" "ai")))
]
""
"and %0, %1, %2 ; %0 = %1 & %2"
[(set_attr "cc" "set_z")])
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_axy" "=a")
(ior:SI
(match_operand:SI 1 "register_axy0" "a0")
(match_operand:SI 2 "nonmemory_axyi" "ai")))
]
""
"or %0, %1, %2 ; %0 = %1 | %2"
[(set_attr "cc" "set_z")])
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_axy" "=a")
(xor:SI
(match_operand:SI 1 "register_axy0" "a0")
(match_operand:SI 2 "nonmemory_axyi" "ai")))
]
""
"xor %0, %1, %2 ; %0 = %1 ^ %2"
[(set_attr "cc" "set_z")])
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_axy" "=a")
(not:SI (match_operand:SI 1 "register_axy" "a")))]
""
"xor %0, %1, -1 ; %0 = ~%1"
[(set_attr "cc" "set_z")])
;;; Shifts. These don't seem to work at all. I think you need a
;;; define_expand for the usual ashift and so on and then define these
;;; patterns for const_int_operand
;;; The current solution works, it just always generates calls to libgcc
;; (define_insn "*ashr_1_bit"
;; [(set (match_operand:SI 0 "register_operand" "=a")
;; (lshiftrt:SI (match_operand:SI 1 "register_operand" "a")
;; (match_operand:SI 2 "const_int_operand" "1")))]
;; ""
;; "lsr %0, %1"
;; [(set_attr "cc" "clobber")])
;; (define_insn "*ashl_1_bit"
;; [(set (match_operand:SI 0 "register_operand" "=a")
;; (ashift:SI (match_operand:SI 1 "register_operand" "a")
;; (match_operand:SI 2 "const_int_operand" "1")))]
;; ""
;; "lsl %0, %1"
;; [(set_attr "cc" "clobber")])
;; MOV Pattern. Change this to a define_expand + a lot of insns to
implement the other datatypes, handle QI, HI, SI and SF at least.
(define_insn "mov<mode>"
[(set (match_operand:SIF 0 "nonimmediate_operand" "=a, a, a, m, a, R,
a, v")
(match_operand:SIF 1 "general_operand" "i, a, m, r, R, a,
v, a"))]
""
"@
or %0, 0, %1 ; %0 = %1
or %0, %1, %1 ; %0 = %1
ld %0, %a1 ; %0 = %a1
st %a0, %1 ; %a0 = %1
mov %0, R0(0) ; %0 = SP
mov R0(0), %1 ; SP = %1
mov %0, %1 ; %0 = %1
mov %0, %1 ; %0 = %1"
[(set_attr "cc" "set_z, set_z, clobber, none, none, none, none, none")])
;;Egge start
;;MOVE Pattern for QI and HI mode
(define_insn "movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=a, m")
(match_operand:QI 1 "general_operand" "m, l"))]
""
"@
ld %0, %a1 ; %0 = %a1
st %a0, %1 ; %a0 = %1"
[(set_attr "cc" "none, none")])
;;(define_insn "movhi"
;; [(set (match_operand:HI 0 "general_operand" "=r,r,m,r")
;; (match_operand:HI 1 "general_operand" "r,m,r,M"))]
;; ""
;; ""
;; []
;;)
;;(define_insn "movqi"
;; [(set (match_operand:QI 0 "general_operand" "=r,r,m,r")
;; (match_operand:QI 1 "general_operand" "r,m,r,M"))]
;; ""
;; ""
;; []
;; )
(define_insn "movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "=a, m")
(match_operand:HI 1 "general_operand" "m, l"))]
""
"@
ld %0, %a1 ; %0 = %a1
st %a0, %1 ; %a0 = %1"
[(set_attr "cc" "none, none")])
;;(define_insn "ashrsi3"
;; [(set (match_operand:SI 0 "register_operand" "=a")
;; (ashiftrt:SI (match_operand:SI 1 "register_operand" "a")
;; (match_operand:SI 2 "general_operand" "ai")))]
;; ""
;; "nop ;shift left"
;; [(set_attr "cc" "set_cz")])
;;(define_insn "ashrdi3"
;; [(set (match_operand:DI 0 "register_operand" "=a")
;; (ashiftrt:DI (match_operand:DI 1 "register_operand" "a")
;; (match_operand:DI 2 "register_operand" "a")))]
;; ""
;; ""
;; [(set_attr "cc" "set_cz")])
;;(define_insn "ashlsi3"
;; [(set (match_operand:SI 0 "register_operand" "=a")
;; (ashift:SI (match_operand:SI 1 "hicovec_reg_or_0" "a0")
;; (match_operand:SI 2 "nonmemory_operand" "ai")))]
;; ""
;; "{ if (GET_CODE (operands[2]) == CONST_INT)
;; return "or %0, %1, %2 ; int";
;; else
;; return "or %0, %1, %2 ; no int";
;; }"
;;[(set_attr "cc" "set_cz")]
;;)
;;(define_insn "umulsidi3"
;; [(set (match_operand:DI 0 "register_operand" "=a")
;; (mult:DI
;; (zero_extend:DI (match_operand:SI 1 "register_operand" "a"))
;; (zero_extend:DI (match_operand:SI 2 "general_operand" "ai"))))]
;; ""
;; "nop"
;; [(set_attr "cc" "set_cz")])
;;Egge end
(define_insn "nop"
[(const_int 0)]
""
"nop"
[(set_attr "cc" "none")])
;; Branches. EQ and NE are defined here, the whole comparison stuff is
more complicated and further down
(define_insn "beq"
[(set (pc)
(if_then_else (eq (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
""
"jz %a0"
[(set_attr "cc" "none")])
(define_insn "bne"
[(set (pc)
(if_then_else (ne (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
""
"jnz %a0"
[(set_attr "cc" "none")])
;; Jumps and Calls
(define_insn "jump"
[(set (pc)
(label_ref (match_operand 0 "" "")))]
""
"jmp [0 + %l0]"
[(set_attr "cc" "none")])
(define_insn "indirect_jump"
[(set (pc)
(match_operand:SI 0 "register_axy" ""))]
""
"jmp [0 + %0]"
[(set_attr "cc" "none")])
(define_insn "call"
[(call (match_operand:SI 0 "memory_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
""
"jal A, %a0 ; call %a1"
[(set_attr "cc" "clobber")])
(define_insn "call_value"
[(set (match_operand 0 "register_a" "")
(call (match_operand:SI 1 "memory_operand" "m")
(match_operand:SI 2 "const_int_operand" "")))]
""
"jal A, %a1 ; A = call %a1"
[(set_attr "cc" "clobber")])
;; epilogue - prologue is defined in hicovec.c. We do our stack
;; unwinding by hand, so we don't need a return pattern. The prologue
;; is simple enough to need no support from gcc, so no custom expander
;; here.
(define_insn "epilogue"
[(return)]
""
"\n\tjmp [0 + __fun_epilogue]"
[(set_attr "cc" "clobber")])
;; Expands for the RTL Generation...
(define_expand "bge"
[(set (pc)
(if_then_else (ge (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"")
(define_expand "bgeu"
[(set (pc)
(if_then_else (geu (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"")
(define_expand "blt"
[(set (pc)
(if_then_else (lt (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"")
(define_expand "bltu"
[(set (pc)
(if_then_else (ltu (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"")
(define_expand "ble"
[(set (pc)
(if_then_else (le (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"")
(define_expand "bleu"
[(set (pc)
(if_then_else (leu (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"")
(define_expand "bgt"
[(set (pc)
(if_then_else (gt (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"")
(define_expand "bgtu"
[(set (pc)
(if_then_else (gtu (cc0) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"")
;; Insns for the assembly generation
(define_insn "branch"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
[(cc0)
(const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))
]
""
"*
return ret_cond_branch (operands[1], 0);"
[(set_attr "cc" "clobber")])
(define_insn "rvbranch"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
[(cc0)
(const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
""
"*
return ret_cond_branch (operands[1], 1);"
[(set_attr "cc" "clobber")])
;; Local variables:
;; mode:emacs-lisp
;; End:
//end .md file
***********************************************************************************************************************
//begin .h file
***********************************************************************************************************************
#ifndef GCC_HICOVEC_H
#define GCC_HICOVEC_H
/* User defines */
#define STORE_REG_NUMBER 0
#define X_REG_NUMBER 1
#define BP_REG_NUMBER 2
#define SP_REG_NUMBER 3
#define LOCAL_LABEL_PREFIX "L"
/* GCC defines */
/*****************************************************************************/
/* CONTROLLING THE DRIVER */
/*****************************************************************************/
#undef STARTFILE_SPEC
#define STARTFILE_SPEC ""
#undef LIB_SPEC
#define LIB_SPEC ""
#undef LIBGCC_SPEC
#define LIBGCC_SPEC ""
/*****************************************************************************/
/* RUN-TIME TARGET SPECIFICATION */
/*****************************************************************************/
#ifndef TARGET_CPU_CPP_BUILTINS
#define TARGET_CPU_CPP_BUILTINS() \
do { \
builtin_define("__HICOVEC__"); \
} while (0)
#endif
#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) 0
/*****************************************************************************/
/* GENERATING CODE FOR PROFILING - NOT IMPLEMENTED */
/*****************************************************************************/
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM, LABELNO) \
{ \
sorry ("Profiler support for Hicovec"); \
}
#ifndef CUMULATIVE_ARGS
struct cumulative_args
{
int ints;
};
#define CUMULATIVE_ARGS struct cumulative_args
#endif
/* REGISTERS */
#define FIRST_PSEUDO_REGISTER 9
/* A: 0
X: 1
Y/BP: 2
SP: 3
R1(0) - R5(0): 4 - 8
*/
#define FIXED_REGISTERS \
{0, 0, 1 ,1, 0, 0, 0, 0, 0}
#define CALL_USED_REGISTERS \
{1, 1, 1, 1, 0, 0, 0, 0, 0}
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
/ UNITS_PER_WORD)
enum reg_class
{
NO_REGS,
GENERAL_REGS,
ARITH_REGS,
SP_REGS,
VEC_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"GENERAL_REGS", \
"ARITH_REGS", \
"SP_REGS", \
"VEC_REGS" \
"ALL_REGS" \
}
/*#define SMALL_REGISTER_CLASSES 1*/
/* Don't change these - It might be useful for optimizing to prefer
register A, but it breaks the register allocator because of too few
registers */
#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
#define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) CLASS
#define REG_CLASS_CONTENTS \
{ \
{0x00000000}, /* NO_REGS */ \
{0x00000001}, /* GENERAL_REGS*/ \
{0x00000007}, /* ARITH_REGS */ \
{0x00000008}, /* SP_REGS */ \
{0x000001F0}, /* VEC_REGS */ \
{0x000001FF} /* ALL_REGS */ \
}
#define REGNO_REG_CLASS(REGNO) hicovec_regno_reg_class(REGNO)
#define BASE_REG_CLASS ARITH_REGS
#define INDEX_REG_CLASS ARITH_REGS
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'l' ? GENERAL_REGS :\
((C) == 'a' ? ARITH_REGS : \
((C) == 'v' ? VEC_REGS : \
((C) == 'R' ? SP_REGS : \
NO_REGS)
#define REG_CLASS_FROM_CONSTRAINT(CHAR, STR)
hicovec_reg_class_from_constraint(CHAR)
#define MAX_REGS_PER_ADDRESS 1
/*****************************************************************************/
/* STACK LAYOUT AND CALLING CONVENTIONS. */
/*****************************************************************************/
#define STACK_GROWS_DOWNWARD 1
#define FRAME_GROWS_DOWNWARD 1
#undef ARGS_GROW_DOWNWARD
/* The Stack pointer points to the last valid var */
#define STACK_POINTER_OFFSET 0
#define STARTING_FRAME_OFFSET -4
#define FIRST_PARM_OFFSET(FNDECL) 8
#define FRAME_POINTER_REQUIRED 1
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) 0
#define STACK_POINTER_REGNUM SP_REG_NUMBER
#define FRAME_POINTER_REGNUM BP_REG_NUMBER
#define ARG_POINTER_REGNUM BP_REG_NUMBER
#define PUSH_ARGS 0
#define AVOID_CCMODE_COPIES
/*****************************************************************************/
/* MISCELLANEOUS PARAMETERS */
/*****************************************************************************/
#define CASE_VECTOR_MODE SImode
#define MOVE_MAX 4
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define FUNCTION_ARG_REGNO_P(x) 0 /*No values can be passed in registers*/
#define FUNCTION_VALUE(VALTYPE, FUNC) \
gen_rtx_REG(TYPE_MODE (VALTYPE), 0)
#define FUNCTION_VALUE_REGNO_P(N) ((N) == STORE_REG_NUMBER)
#define RETURN_POPS_ARGS(FNDECL, FUNTYPE, SIZE) 0
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 0
#define HARD_REGNO_MODE_OK(REGNO, MODE)
hicovec_hard_regno_mode_ok(REGNO, MODE)
#define MODES_TIEABLE_P(MODE1, MODE2) 0
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, STORE_REG_NUMBER)
/*****************************************************************************/
/* TRAMPOLINES FOR NESTED FUNCTIONS - NOT SUPPORTED */
/*****************************************************************************/
#define TRAMPOLINE_SIZE 32
#define INITIALIZE_TRAMPOLINE(addr, fnaddr, static_chain) \
{ \
sorry ("Trampoline support for HiCoVec"); \
}
#define SLOW_BYTE_ACCESS 1
#define NOTICE_UPDATE_CC(EXT, INSN) hicovec_notice_update_cc(EXT,INSN)
#define CLASS_MAX_NREGS(CLASS, MODE) 1
#define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE, C, STR) 0
#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) 0
/*****************************************************************************/
/* ADDRESSING MODES */
/*****************************************************************************/
#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
#define HAVE_POST_INCREMENT 0
#define HAVE_POST_DECREMENT 0
#define HAVE_POST_MODIFY_DISP 0
#define HAVE_POST_MODIFY_REG 0
#define REGNO_OK_FOR_BASE_P(REGNO) ((REGNO) < 3)
#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
#ifdef REG_OK_STRICT
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
#else
#define REG_OK_FOR_BASE_P(X) 1
#define REG_OK_FOR_INDEX_P(X) 1
#endif
#ifdef REG_OK_STRICT
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
{ \
if (hicovec_legitimate_address_p (MODE, X, 1)) \
goto LABEL; \
}
#else
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
{ \
if (hicovec_legitimate_address_p (MODE, X, 0)) \
goto LABEL; \
}
#endif /* REG_OK_STRICT */
#define LEGITIMATE_CONSTANT_P(X) ((INTVAL(X) <0x8000) && (INTVAL(X) >=
-0x8000))
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
/*****************************************************************************/
/* LAYOUT OF SOURCE LANGUAGE DATA TYPES */
/*****************************************************************************/
#define Pmode SImode
#define FUNCTION_MODE SImode
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN 0
#define WORDS_BIG_ENDIAN 0
#define UNITS_PER_WORD 4
#define BITS_PER_UNIT 8
#define POINTER_SIZE 32
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 32
#define FUNCTION_BOUNDARY 32
#define STRUCTURE_SIZE_BOUNDARY 32
#define BIGGEST_ALIGNMENT 32
#define BASIC_ALIGNMENT 32
#define STRICT_ALIGNMENT 1
#define CHAR_TYPE_SIZE 8
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE 32
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 32
#define LONG_DOUBLE_TYPE_SIZE 32
#define DEFAULT_SIGNED_CHAR 1
#define SIZE_TYPE "unsigned int"
#define PTRDIFF_TYPE "unsigned int"
/*TODO Egge libgcc2
#define MAX_FIXED_MODE_SIZE 32
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 32*/
/*****************************************************************************/
/* ASSEMBLER FORMAT */
/*****************************************************************************/
#define GLOBAL_ASM_OP "\t.globl\t"
#undef ASM_APP_ON
#define ASM_APP_ON ";APP\n"
#undef ASM_APP_OFF
#define ASM_APP_OFF ";NO_APP\n"
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
asm_fprintf ((STREAM), "\n")
#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
{ \
int i; \
for(i=0;i<(NBYTES);i++) \
fprintf((STREAM),".dc 0"); \
}
#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
do { \
int i; \
fputs ("\n;.comm \n",
(FILE)); \
assemble_name ((FILE), (NAME)); \
fprintf ((FILE), ":\n"); \
for(i = 0; i < ROUNDED; i++) \
fprintf ((FILE), ".dc 0\n"); \
} while(0)
#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
do { \
int i; \
fputs ("\n;.lcomm \n",
(FILE)); \
assemble_name ((FILE), (NAME)); \
fprintf ((FILE), ":\n"); \
for(i = 0; i < ROUNDED; i++) \
fprintf ((FILE), ".dc 0\n"); \
} while(0)
#define TEXT_SECTION_ASM_OP ""
#define DATA_SECTION_ASM_OP ""
#define BSS_SECTION_ASM_OP ""
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
asm_fprintf ((STREAM), "\t.dc\t.0x%x\n", (VALUE))
#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
do { \
int i; \
for(i = 0; i < LEN; i++) \
fprintf(STREAM, ".dc 0x%x\n", PTR[i] & 0xff); \
fprintf(STREAM, ".dc 0\n"); \
} while (0)
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
/*****************************************************************************/
/* INSTRUCTION OUTPUT */
/*****************************************************************************/
#define REGISTER_NAMES \
{ \
"A", "X", "Y", "SP", "R1(0)", "R2(0)", "R3(0)", "R4(0)", "R5(0)"\
}
#define PRINT_OPERAND(STREAM, X, CODE) hicovec_print_operand(STREAM, X,
CODE)
#define PRINT_OPERAND_ADDRESS(STREAM, ADDR)
hicovec_print_operand_address(STREAM, ADDR)
/*****************************************************************************/
/* OUTPUT OF DISPATCH TABLES */
/*****************************************************************************/
/*TODO
#include "hicovec-protos.h"*/
#if defined(__STDC__) || defined(ALMOST_STDC)
#define AS2(a,b,c) #a " " #b "," #c
#define AS2C(b,c) " " #b "," #c
#define AS3(a,b,c,d) #a " " #b "," #c "," #d
#define AS1(a,b) #a " " #b
#else
#define AS1(a,b) "a b"
#define AS2(a,b,c) "a b,c"
#define AS2C(b,c) " b,c"
#define AS3(a,b,c,d) "a b,c,d"
#endif
#define OUT_AS1(a,b) output_asm_insn (AS1(a,b), operands)
#define OUT_AS2(a,b,c) output_asm_insn (AS2(a,b,c), operands)
#define CR_TAB "\n\t"
/* Taken from Alpha - Doesn't work for us, as we can't swap immediates.
Feel free to fix this */
/* #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ */
/* do { \ */
/* if (((CODE) == LE || (CODE) == GT || (CODE) == LEU || (CODE) ==
GTU)) \ */
/* { \ */
/* rtx tem = (OP0); \ */
/* (OP0) = (OP1); \ */
/* (OP1) = tem; \ */
/* (CODE) = reverse_condition (CODE); \ */
/* } \ */
/* } while (0) */
/* /\* && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
*\/ */
const char * ret_cond_branch (rtx x, int reverse);
#endif
//end .h file
***********************************************************************************************************************
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