From: Michael Eager <eager@eagerm.com>
To: gcc@gcc.gnu.org
Subject: Re: Getting DWARF codes from RTX
Date: Thu, 20 Oct 2011 18:59:00 -0000 [thread overview]
Message-ID: <4EA065CE.6080503@eagerm.com> (raw)
In-Reply-To: <2950715866004049A240A2F9BB410E7315FB115F5C@azsmsx502.amr.corp.intel.com>
On 10/20/2011 06:53 AM, Iyer, Balaji V wrote:
> So, I need the equivalent dwarf code (in hex) for DW_OP_REG1, DW_OP_REG2 and DW_OP_REG3, so that a dwarf decoder can decode it correctly.
It's not clear what you mean by the dwarf code for DW_OP_REG1, etc.
Encoding for DW_OP_REG1, etc., is described in the Dwarf Standard on page 166.
See http://dwarfstd.org.
If you are looking for translation between gcc register numbers
and the Dwarf register numbers, look in dwarf2out.c. Search for DBX_REGISTER_NUMBER.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
next prev parent reply other threads:[~2011-10-20 18:18 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-20 5:43 Iyer, Balaji V
2011-10-20 8:13 ` Ian Lance Taylor
2011-10-20 14:41 ` Iyer, Balaji V
2011-10-20 18:59 ` Michael Eager [this message]
2011-10-20 21:11 ` Ian Lance Taylor
2011-10-20 22:46 ` Iyer, Balaji V
2011-10-21 6:09 ` Ian Lance Taylor
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