From: Richard Henderson <rth@redhat.com>
To: Paul_Koning@Dell.com
Cc: paulo@matos-sorge.com, gcc@gcc.gnu.org
Subject: Re: Expanding instructions with condition codes inter-deps
Date: Mon, 24 Oct 2011 07:04:00 -0000 [thread overview]
Message-ID: <4EA48541.8000100@redhat.com> (raw)
In-Reply-To: <09787EF419216C41A903FD14EE5506DD030CE5DD38@AUSX7MCPC103.AMER.DELL.COM>
On 10/21/2011 05:49 PM, Paul_Koning@Dell.com wrote:
>> There are lots of parts of the compiler that don't optimize well when an insn has more than one output. For the normal insn, just clobber the flags; don't include a second SET.
>
> Yes, but... isn't the whole point of CC modeling that you can take advantage of the CC left around by an instruction? Typically in machines with condition codes, you can eliminate test instructions (compare with zero) if the previous instruction has that variable as its output. But if we're discouraged from writing insns with CC outputs as normal practice, and if the compiler doesn't handle such constructs well in optimization, what then?
The solution is to have *two* insn patterns, one with a set of the flags
and one with only a clobber. Have a look through i386.md and
how the flags register is handled there.
r~
next prev parent reply other threads:[~2011-10-23 21:21 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-17 15:58 Paulo J. Matos
2011-10-17 17:23 ` Andrew Pinski
2011-10-18 13:44 ` Paulo J. Matos
2011-10-19 5:22 ` Richard Henderson
2011-10-19 5:45 ` Paul_Koning
[not found] ` <CAPOJ94M2XrqM_kG98v1dC1=K2fEkHpuNLSkZBrQyzJ9ncmaQXg@mail.gmail.com>
2011-10-21 20:57 ` Richard Henderson
2011-10-21 21:42 ` Paulo J. Matos
2011-10-22 0:13 ` Richard Henderson
2011-10-22 5:13 ` Peter Bigot
2011-10-22 5:21 ` Paul_Koning
2011-10-24 7:04 ` Richard Henderson [this message]
2011-10-24 12:12 ` Paulo J. Matos
2011-10-24 12:07 ` Paulo J. Matos
2011-10-20 12:46 ` Paulo J. Matos
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