From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) by sourceware.org (Postfix) with ESMTPS id 2C23638930D2 for ; Wed, 22 Jul 2020 07:48:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 2C23638930D2 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=suse.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jbeulich@suse.com X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 5FD9FACAF; Wed, 22 Jul 2020 07:48:47 +0000 (UTC) Subject: Re: New x86-64 micro-architecture levels To: Florian Weimer Cc: "Mallappa, Premachandra" , "libc-alpha@sourceware.org" , "gcc@gcc.gnu.org" , "llvm-dev@lists.llvm.org" , "x86-64-abi@googlegroups.com" , "H.J. Lu" , "matz@suse.de" , Tom Stellard , Jeff Law References: <87365zz3a6.fsf@oldenburg2.str.redhat.com> <87imegn3s0.fsf@oldenburg2.str.redhat.com> From: Jan Beulich Message-ID: <56416707-0578-6e87-ff26-6075ce6fda94@suse.com> Date: Wed, 22 Jul 2020 09:48:40 +0200 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <87imegn3s0.fsf@oldenburg2.str.redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3032.7 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Jul 2020 07:48:42 -0000 On 21.07.2020 20:04, Florian Weimer wrote: > * Premachandra Mallappa: > >> [AMD Public Use] >> >> Hi Floarian, >> >>> I'm including a proposal for the levels below. I use single letters for them, but I expect that the concrete implementation of this proposal will use >>> names like “x86-100”, “x86-101”, like in the glibc patch referenced above. (But we can discuss other approaches.) >> >> Personally I am not a big fan of this, for 2 reasons >> 1. uses just x86 in name on x86_64 as well > > That's deliberate, so that we can use the same x86-* names for 32-bit > library selection (once we define matching micro-architecture levels > there). While indeed I did understand it to be deliberate, in the light of 64-bit only ISA extensions (like AMX, and I suspect we're going to see more) I nevertheless think Premachandra has a point here. Jan