From: Richard Earnshaw <Richard.Earnshaw@foss.arm.com>
To: Surya Kumari Jangala <jskumari@linux.vnet.ibm.com>,
Richard Sandiford <richard.sandiford@arm.com>,
Peter Bergner <bergner@linux.ibm.com>
Cc: GCC Development <gcc@gcc.gnu.org>, vmakarov@redhat.com
Subject: Re: Discussion about arm testcase failures seen with patch for PR111673
Date: Fri, 24 Nov 2023 10:48:44 +0000 [thread overview]
Message-ID: <566f7575-10c1-42b7-b006-f77a631a20cb@foss.arm.com> (raw)
In-Reply-To: <2a2060c7-5288-422d-ba1d-dfe4306b4c3f@linux.vnet.ibm.com>
On 24/11/2023 08:09, Surya Kumari Jangala via Gcc wrote:
> Hi Richard,
> Ping. Please let me know if the test failure that I mentioned in the mail below can be handled by changing the expected generated code. I am not conversant with arm, and hence would appreciate your help.
>
> Regards,
> Surya
>
> On 03/11/23 4:58 pm, Surya Kumari Jangala wrote:
>> Hi Richard,
>> I had submitted a patch for review (https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631849.html)
>> regarding scaling save/restore costs of callee save registers with block
>> frequency in the IRA pass (PR111673).
>>
>> This patch has been approved by VMakarov
>> (https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632089.html).
>>
>> With this patch, we are seeing performance improvements with spec on x86
>> (exchange: 5%, xalancbmk: 2.5%) and on Power (perlbench: 5.57%).
>>
>> I received a mail from Linaro about some failures seen in the CI pipeline with
>> this patch. I have analyzed the failures and I wish to discuss the analysis with you.
>>
>> One failure reported by the Linaro CI is:
>>
>> FAIL: gcc.target/arm/pr111235.c scan-assembler-times ldrexd\tr[0-9]+, r[0-9]+, \\[r[0-9]+\\] 2
>>
>> The diff in the assembly between trunk and patch is:
>>
>> 93c93
>> < push {r4, r5}
>> ---
>>> push {fp}
>> 95c95
>> < ldrexd r4, r5, [r0]
>> ---
>>> ldrexd fp, ip, [r0]
>> 99c99
>> < pop {r4, r5}
>> ---
>>> ldr fp, [sp], #4
>>
>>
>> The test fails with patch because the ldrexd insn uses fp & ip registers instead
>> of r[0-9]+
>>
>> But the code produced by patch is better because it is pushing and restoring only
>> one register (fp) instead of two registers (r4, r5). Hence, this test can be
>> modified to allow it to pass on arm. Please let me know what you think.
>>
>> If you need more information, please let me know. I will be sending separate mails
>> for the other test failures.
>>
Thanks for looking at this.
The key part of this test is that the compiler generates LDREXD. The
registers used for that are pretty much irrelevant as we don't match
them to any other operations within the test. So I'd recommend just
testing for the mnemonic and not for any of the operands (ie just match
"ldrexd\t").
R.
>> Regards,
>> Surya
>>
>>
>>
next prev parent reply other threads:[~2023-11-24 10:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-03 11:28 Surya Kumari Jangala
2023-11-24 8:09 ` Surya Kumari Jangala
2023-11-24 10:48 ` Richard Earnshaw [this message]
2023-11-28 12:52 ` Discussion about arm/aarch64 " Surya Kumari Jangala
2023-11-28 13:48 ` Richard Earnshaw
2023-11-28 15:41 ` Richard Sandiford
2023-12-14 7:17 ` Surya Kumari Jangala
2023-12-14 16:11 ` Richard Earnshaw (lists)
2023-12-15 17:04 ` Surya Kumari Jangala
2024-01-29 6:14 ` Surya Kumari Jangala
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