SPE scalar float instructions

SPE scalar float instructions

[Zack Weinberg]

Currently, the SPE scalar float instructions are predicated on
TARGET_HARD_FLOAT && !TARGET_FPRS (and TARGET_E500_DOUBLE for DFmode)
but not on TARGET_SPE.  This can cause problems in an embedded context
- as one of CodeSourcery's customers points out,

> This will indeed post a problem, because those instructions require
> MSR[SPE] bit be set, which is not true for all cases.  SPE unavailable
> exception may result.

I'm wondering if TARGET_SPE should be added to the controlling
condition for all those instructions.  Thoughts?

zw

Re: SPE scalar float instructions

[Kumar Gala]

Zack,

Not sure what TARGET_SPE implies (Aldy should know :)

However, we did want to keep the SPE scalar float usage separate from 
the SPE vector instructions.  Its feasible and possible that Freescale 
may release a processor that implements only the scalar floating point 
instructions and not the SIMD instructions.

- kumar

On Dec 14, 2004, at 9:42 PM, Zack Weinberg wrote:

>
>
> Currently, the SPE scalar float instructions are predicated on
>  TARGET_HARD_FLOAT && !TARGET_FPRS (and TARGET_E500_DOUBLE for DFmode)
>  but not on TARGET_SPE.  This can cause problems in an embedded context
>  - as one of CodeSourcery's customers points out,
>
> > This will indeed post a problem, because those instructions require
>  > MSR[SPE] bit be set, which is not true for all cases.  SPE 
> unavailable
>  > exception may result.
>
> I'm wondering if TARGET_SPE should be added to the controlling
>  condition for all those instructions.  Thoughts?
>
> zw

Re: SPE scalar float instructions

[Aldy Hernandez]

On Tue, Dec 14, 2004 at 07:42:19PM -0800, Zack Weinberg wrote:
> 
> Currently, the SPE scalar float instructions are predicated on
> TARGET_HARD_FLOAT && !TARGET_FPRS (and TARGET_E500_DOUBLE for DFmode)
> but not on TARGET_SPE.  This can cause problems in an embedded context
> - as one of CodeSourcery's customers points out,
> 
> > This will indeed post a problem, because those instructions require
> > MSR[SPE] bit be set, which is not true for all cases.  SPE unavailable
> > exception may result.

I'm not sure I follow the above? (??)

> 
> I'm wondering if TARGET_SPE should be added to the controlling
> condition for all those instructions.  Thoughts?

As Kumar mentioned, a there may be a chip with SPE but not FP in the
GPRs.

Also, suppose you have -mspe=yes -mfloat-gprs=no (or the opposite).

Aldy

Re: SPE scalar float instructions

[Kumar Gala]

On Dec 15, 2004, at 10:59 AM, Aldy Hernandez wrote:

> On Tue, Dec 14, 2004 at 07:42:19PM -0800, Zack Weinberg wrote:
>  >
> > Currently, the SPE scalar float instructions are predicated on
>  > TARGET_HARD_FLOAT && !TARGET_FPRS (and TARGET_E500_DOUBLE for 
> DFmode)
>  > but not on TARGET_SPE.  This can cause problems in an embedded 
> context
>  > - as one of CodeSourcery's customers points out,
>  >
> > > This will indeed post a problem, because those instructions require
>  > > MSR[SPE] bit be set, which is not true for all cases.  SPE 
> unavailable
>  > > exception may result.

I missed this last time, and agree with aldy ??? -- on know on e500 
there is an errata (that may not be fixed) with regards to causing an 
exception for the set of instructions, however the architecture 
specifies that the efs* instructions should NOT require MSR[SPE] to be 
set.  I'm looking into if and when this may be fixed on e500.  However, 
its not clear what the implication is to your customer.

>
> I'm not sure I follow the above? (??)
>
> >
> > I'm wondering if TARGET_SPE should be added to the controlling
>  > condition for all those instructions.  Thoughts?
>
> As Kumar mentioned, a there may be a chip with SPE but not FP in the
>  GPRs.
>
> Also, suppose you have -mspe=yes -mfloat-gprs=no (or the opposite).
>
> Aldy
>

- kumar