From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 103556 invoked by alias); 10 Dec 2019 20:16:50 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 103546 invoked by uid 89); 10 Dec 2019 20:16:49 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_NEUTRAL autolearn=no version=3.3.1 spammy=disablenls, disable-nls, ira, withdwarf2 X-HELO: mo4-p05-ob.smtp.rzone.de Received: from mo4-p05-ob.smtp.rzone.de (HELO mo4-p05-ob.smtp.rzone.de) (85.215.255.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 10 Dec 2019 20:16:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1576009005; s=strato-dkim-0002; d=gjlay.de; h=In-Reply-To:References:Subject:To:From:Date:Message-ID: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=nVwRtG8yRoqst8wNl2vF9br9GBaZwSa4tEtRXP54rsQ=; b=HW+fCQXnzMAaca1v5LI0pXpoz7qnEpV+DUUNEbNG1W6irWJSa60a9Ox9XtU7YnIub7 6MYWNsS1OOgSxLHxjTjVeer/tHE8CaVy/vmMhf8Wq4CpRnDSLAxENS6jbMGfu7yWkmer 43V44iWcz1CX93KaUIdWw7gf+IJ8uf1N/b1d6G3JjZ+7wx1Jmv2Hxo1RZoG1eWXHqH2i eP7w4OKsR+mTDgtec96FLs5l1QbDn//gSVKaSGxVRXZx5Vg3IEYR4Zu1F4MgUJ4zwX7v ZaDENsKbKA8qaMQxT2LyhpGM1LGOlwgj1e6HWTosaQsBLThPUqOd/JZ5XqGE3xhDaDtu 44hQ== Received: from [192.168.2.100] by smtp.strato.de (RZmta 46.0.2 DYNA|AUTH) with ESMTPSA id N0821bvBAKGiA9f (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (curve X9_62_prime256v1 with 256 ECDH bits, eq. 3072 bits RSA)) (Client did not present a certificate) for ; Tue, 10 Dec 2019 21:16:44 +0100 (CET) Message-ID: <5DEFFCD4.4080903@gcc.gnu.org> Date: Tue, 10 Dec 2019 20:16:00 -0000 From: Georg-Johann Lay User-Agent: Thunderbird 2.0.0.24 (Windows/20100228) MIME-Version: 1.0 To: gcc@gcc.gnu.org Subject: Re: Code bloat due to silly IRA cost model? References: <47b10439-21b8-81f6-3838-a2bcd0fa8048@gjlay.de> In-Reply-To: <47b10439-21b8-81f6-3838-a2bcd0fa8048@gjlay.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2019-12/txt/msg00159.txt.bz2 Hi, doesn't actually anybody know know to make memory more expensive than registers when it comes to allocating registers? Whatever I am trying for TARGET_MEMORY_MOVE_COST and TARGET_REGISTER_MOVE_COST, ira-costs.c always makes registers more expensive than mem and therefore allocates values to stack slots instead of keeping them in registers. Test case (for avr) is as simple as it gets: float func (float); float call (float f) { return func (f); } What am I missing? Johann Georg-Johann Lay schrieb: > Hi, > > I am trying to track down a code bloat issue and am stuck because I do > not understand IRA's cost model. > > The test case is as simple as it gets: > > float func (float); > > float call (float f) > { > return func (f); > } > > IRA dump shows the following insns: > > > (insn 14 4 2 2 (set (reg:SF 44) > (reg:SF 22 r22 [ f ])) "bloat.c":4:1 85 {*movsf} > (expr_list:REG_DEAD (reg:SF 22 r22 [ f ]) > (nil))) > (insn 2 14 3 2 (set (reg/v:SF 43 [ f ]) > (reg:SF 44)) "bloat.c":4:1 85 {*movsf} > (expr_list:REG_DEAD (reg:SF 44) > (nil))) > (note 3 2 6 2 NOTE_INSN_FUNCTION_BEG) > (insn 6 3 7 2 (set (reg:SF 22 r22) > (reg/v:SF 43 [ f ])) "bloat.c":5:12 85 {*movsf} > (expr_list:REG_DEAD (reg/v:SF 43 [ f ]) > (nil))) > (call_insn/j 7 6 8 2 (parallel [ > > #14 sets pseudo 44 from arg register R22. > #2 moves it to pseudo 43 > #6 moves it to R22 as it prepares for call_insn #7. > > There are 2 allocnos and cost: > > Pass 0 for finding pseudo/allocno costs > > a1 (r44,l0) best NO_REGS, allocno NO_REGS > a0 (r43,l0) best NO_REGS, allocno NO_REGS > > a0(r43,l0) costs: ADDW_REGS:32000 SIMPLE_LD_REGS:32000 LD_REGS:32000 > NO_LD_REGS:32000 GENERAL_REGS:32000 MEM:9000 > a1(r44,l0) costs: ADDW_REGS:32000 SIMPLE_LD_REGS:32000 LD_REGS:32000 > NO_LD_REGS:32000 GENERAL_REGS:32000 MEM:9000 > > which is quite odd because MEM is way more expensive here than any REG. > > Okay, so let's boost the MEM cost (TARGET_MEMORY_MOVE_COST) by a factor > of 100: > > a1 (r44,l0) best NO_REGS, allocno NO_REGS > a0 (r43,l0) best NO_REGS, allocno NO_REGS > > a0(r43,l0) costs: ADDW_REGS:3200000 SIMPLE_LD_REGS:3200000 > LD_REGS:3200000 NO_LD_REGS:3200000 GENERAL_REGS:3200000 MEM:801000 > a1(r44,l0) costs: ADDW_REGS:3200000 SIMPLE_LD_REGS:3200000 > LD_REGS:3200000 NO_LD_REGS:3200000 GENERAL_REGS:3200000 MEM:801000 > > What??? The REG costs are 100 times higher, and stille higher that the > MEM costs. What the heck is going on? > > Setting TARGET_REGISTER_MOVE_COST and also TARGET_MEMORY_MOVE_COST to 0 > yiels: > > a0(r43,l0) costs: ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 > GENERAL_REGS:0 MEM:0 > a1(r44,l0) costs: ADDW_REGS:0 SIMPLE_LD_REGS:0 LD_REGS:0 NO_LD_REGS:0 > GENERAL_REGS:0 MEM:0 > > as expected, i.e. there is no other hidden source of costs considered by > IRA. And even TARGET_REGISTER_MOVE_COST = 0 and > TARGET_MEMORY_MOVE_COST = original gives: > > a0(r43,l0) costs: ADDW_REGS:32000 SIMPLE_LD_REGS:32000 LD_REGS:32000 > NO_LD_REGS:32000 GENERAL_REGS:32000 MEM:9000 > a1(r44,l0) costs: ADDW_REGS:32000 SIMPLE_LD_REGS:32000 LD_REGS:32000 > NO_LD_REGS:32000 GENERAL_REGS:32000 MEM:9000 > > How the heck do I tell ira-costs that registers are way cheaper than MEM? > > Johann > > > p.s. > > test case compiled with > > $ avr-gcc bloat.c -S -Os -dp -da -fsplit-wide-types-early -v > > Target: avr > Configured with: ../../gcc.gnu.org/trunk/configure --target=avr > --prefix=/local/gnu/install/gcc-10 --disable-shared --disable-nls > --with-dwarf2 --enable-target-optspace=yes --with-gnu-as --with-gnu-ld > --enable-checking=release --enable-languages=c,c++ --disable-gcov > Thread model: single > Supported LTO compression algorithms: zlib > gcc version 10.0.0 20191021 (experimental) (GCC)