From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7011 invoked by alias); 25 Mar 2008 14:19:40 -0000 Received: (qmail 6999 invoked by uid 22791); 25 Mar 2008 14:19:39 -0000 X-Spam-Check-By: sourceware.org Received: from rv-out-0910.google.com (HELO rv-out-0910.google.com) (209.85.198.189) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 25 Mar 2008 14:19:18 +0000 Received: by rv-out-0910.google.com with SMTP id g11so1932419rvb.56 for ; Tue, 25 Mar 2008 07:19:16 -0700 (PDT) Received: by 10.141.88.3 with SMTP id q3mr3325593rvl.46.1206454755938; Tue, 25 Mar 2008 07:19:15 -0700 (PDT) Received: by 10.141.161.18 with HTTP; Tue, 25 Mar 2008 07:19:15 -0700 (PDT) Message-ID: <5afce4f40803250719n6ffd09c6h9ad4481ff7afdaf5@mail.gmail.com> Date: Tue, 25 Mar 2008 14:56:00 -0000 From: "Jan Hoogerbrugge" To: gcc@gcc.gnu.org Subject: subreg question MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2008-03/txt/msg00969.txt.bz2 Hi, My target architecture has 32 bit registers and uses register pairs for 64 bit values. What makes it special is that whenever a register pair is written by a 64 bit operation, the individual registers should not be read by 32 bit operations. The reverse is also true: whenever a register pair is used as 64 bit operand, the value should not be produced by 32 bit operations. In order to connect 64 to 32 operations, the target architecture provides high and low, which select a register from a register pair, and combine, which combines two registers into a register pair. How to tell gcc to insert high, low, and combine operations, when 32 and 64 bit operations are exchanging values? Regards, Jan