From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26218 invoked by alias); 23 Sep 2009 22:58:00 -0000 Received: (qmail 26209 invoked by uid 22791); 23 Sep 2009 22:57:59 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,SARE_MSGID_LONG40,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mail-ew0-f226.google.com (HELO mail-ew0-f226.google.com) (209.85.219.226) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 23 Sep 2009 22:57:56 +0000 Received: by ewy26 with SMTP id 26so1175526ewy.29 for ; Wed, 23 Sep 2009 15:57:54 -0700 (PDT) MIME-Version: 1.0 Received: by 10.216.88.136 with SMTP id a8mr581724wef.77.1253746674195; Wed, 23 Sep 2009 15:57:54 -0700 (PDT) In-Reply-To: <863b0cbf0908081459u33e84018h2e2b6cf871d9be5c@mail.gmail.com> References: <863b0cbf0908081459u33e84018h2e2b6cf871d9be5c@mail.gmail.com> Date: Wed, 23 Sep 2009 22:58:00 -0000 Message-ID: <6dc9ffc80909231557n21c84e62v3961248a9ddcbc97@mail.gmail.com> Subject: Re: Request for code review - (ZEE patch : Redundant Zero extension elimination) From: "H.J. Lu" To: Sriraman Tallam Cc: gcc@gcc.gnu.org, Ian Lance Taylor , Diego Novillo Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2009-09/txt/msg00485.txt.bz2 On Sat, Aug 8, 2009 at 2:59 PM, Sriraman Tallam wrote: > Hi, > > =A0 =A0Here is a patch to eliminate redundant zero-extension instructions > on x86_64. > > Tested: Ran the gcc regresssion testsuite on x86_64-linux and verified > that the results are the same with/without this patch. > > > Problem Description : > --------------------------------- > > This pass is intended to be applicable only to targets that implicitly > zero-extend 64-bit registers after writing to their lower 32-bit half. > For instance, x86_64 zero-extends the upper bits of a register > implicitly whenever an instruction writes to its lower 32-bit half. > For example, the instruction *add edi,eax* also zero-extends the upper > 32-bits of rax after doing the addition. =A0These zero extensions come > for free and GCC does not always exploit this well. =A0That is, it has > been observed that there are plenty of cases where GCC explicitly > zero-extends registers for x86_64 that are actually useless because > these registers were already implicitly zero-extended in a prior > instruction. =A0This pass tries to eliminate such useless zero extension > instructions. > Does this fix: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D17387 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D34653 --=20 H.J.