From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24338 invoked by alias); 18 Mar 2010 13:20:33 -0000 Received: (qmail 24327 invoked by uid 22791); 18 Mar 2010 13:20:29 -0000 X-SWARE-Spam-Status: No, hits=-1.0 required=5.0 tests=AWL,BAYES_00,SARE_MSGID_LONG40 X-Spam-Check-By: sourceware.org Received: from mail-pw0-f47.google.com (HELO mail-pw0-f47.google.com) (209.85.160.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 18 Mar 2010 13:20:25 +0000 Received: by pwi6 with SMTP id 6so1482439pwi.20 for ; Thu, 18 Mar 2010 06:20:23 -0700 (PDT) MIME-Version: 1.0 Received: by 10.142.207.17 with SMTP id e17mr1275775wfg.120.1268918422910; Thu, 18 Mar 2010 06:20:22 -0700 (PDT) In-Reply-To: References: <714984df1003170555m6d38cf46y2b916f52ef6fa3f0@mail.gmail.com> Date: Thu, 18 Mar 2010 13:43:00 -0000 Message-ID: <714984df1003180620s21d650f8p1489d4d5232c1068@mail.gmail.com> Subject: Re: Is it possible to port GCC backend to a architecture with very limited hard registers? From: redriver jiang To: Ian Lance Taylor Cc: gcc@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2010-03/txt/msg00253.txt.bz2 Ok. Thanks! Then I will persuade the guys who develop the MCU to add one or more base registers to ease the reload problem, and besides, I will add some virtual registers( who are static "memory".) to hold 16,32 bit mode variables.Hope these 2 solutions can make better codes. Now I just begin to build a prototype porting. 2010/3/18 Ian Lance Taylor : > redriver jiang writes: > >> Right now I attempts to port the GCC backend to a MCU with very >> limited hard registers: only one 8 bit ACC reg, one 16 bit base reg >> for addressing, one stats reg. >> I searched the GCC backend porting, and seems 68HC1X has the similar >> scene, but it use many "ram simulated" register. I wonder that if it >> is possbile to provided thislimited 3 register to GCC bankend, and let >> all 16bit(HImode), 32bit(SImode) operands spilled to stack. > > It should be possible, though it owuld not be easy to resolve all the > reload issues. =A0gcc will not generate particularly good code for such > a processor; you will see an awful lot of register shuffling. > > Ian >