From: "Fu, Chao-Ying" <fu@mips.com>
To: Chung-Lin Tang <cltang@codesourcery.com>,
Mingjie Xing <mingjie.xing@gmail.com>,
"gcc@gcc.gnu.org" <gcc@gcc.gnu.org>,
Richard Sandiford <rdsandiford@googlemail.com>
Cc: "Fuhler, Rich" <rich@mips.com>
Subject: RE: [MIPS] Test case dspr2-MULT is failed
Date: Fri, 18 Feb 2011 01:19:00 -0000 [thread overview]
Message-ID: <7C6479EB2BF52547AC332FD6034646DA8495BF8A@exchdb01.mips.com> (raw)
In-Reply-To: <4D260AC3.8080105@codesourcery.com>
Chung-Lin Tang wrote:
> I analyzed this testcase regression a while earlier; the
> direct cause of
> this is due to mips_order_regs_for_local_alloc(), which now serves as
> MIPS' ADJUST_REG_ALLOC_ORDER macro.
>
> The mips_order_regs_for_local_alloc() function seems to be written for
> the old local-alloc.c, still left as the deprecated
> ORDER_REGS_FOR_LOCAL_ALLOC macro after the transition to IRA (actually
> not called at all during then), and relatively recently
> 'revived' after
> a patch by Bernd that created the ADJUST_REG_ALLOC_ORDER
> macro went in.
>
> So you have a local-alloc.c heuristic working in IRA, which seemed to
> cause these regressions.
>
> Removing mips_order_regs_for_local_alloc() will let this
> testcase pass;
> of course the real fix should be to review the MIPS
> reg-ordering logic,
> left for you MIPS people...
I think your analysis is correct. We should just delete mips_order_regs_for_local_alloc()
in mips.c and delete ADJUST_REG_ALLOC_ORDER in mips.h.
Then, 3 accumulators can be used in dspr2-MULT.c and dspr2-MULTU.c now. Thanks!
Ex:
/* Test MIPS32 DSP REV 2 MULT instruction. Tune for a CPU that has
pipelined mult. */
/* { dg-do compile } */
/* { dg-options "-mgp32 -mdspr2 -O2 -ffixed-hi -ffixed-lo -mtune=74kc" } */
/* { dg-final { scan-assembler "\tmult\t" } } */
/* { dg-final { scan-assembler "ac1" } } */
/* { dg-final { scan-assembler "ac2" } } */
/* { dg-final { scan-assembler "ac3" } } */
typedef long long a64;
NOMIPS16 a64 test (a64 *a, int *b, int *c)
{
a[0] = (a64) b[0] * c[0];
a[1] = (a64) b[1] * c[1];
a[2] = (a64) b[2] * c[2];
}
Ex:
/* Test MIPS32 DSP REV 2 MULTU instruction. Tune for a CPU that has
pipelined multu. */
/* { dg-do compile } */
/* { dg-options "-mgp32 -mdspr2 -O2 -ffixed-hi -ffixed-lo -mtune=74kc" } */
/* { dg-final { scan-assembler "\tmultu\t" } } */
/* { dg-final { scan-assembler "ac1" } } */
/* { dg-final { scan-assembler "ac2" } } */
/* { dg-final { scan-assembler "ac3" } } */
typedef unsigned long long a64;
NOMIPS16 a64 test (a64 *a, unsigned int *b, unsigned int *c)
{
a[0] = (a64) b[0] * c[0];
a[1] = (a64) b[1] * c[1];
a[2] = (a64) b[2] * c[2];
}
Regards,
Chao-ying
next prev parent reply other threads:[~2011-02-17 23:05 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-29 8:14 Mingjie Xing
2010-12-31 13:38 ` Richard Sandiford
2011-01-06 18:32 ` Chung-Lin Tang
2011-01-13 5:50 ` Mingjie Xing
2011-02-18 1:19 ` Fu, Chao-Ying [this message]
2011-02-18 6:21 ` Mingjie Xing
2011-02-18 6:43 ` Fu, Chao-Ying
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