RFC: new rtl vec_set_unit/vec_get_unit

[Aldy Hernandez <aldyh@redhat.com>]

I can't seem to find the original thread on the GCC archive, but... 
there was a discussion a while back between Jan, Richard, and me about 
subregs of SIMD types creating bogus code.

Particularly, when we have a hard register, both of the following 
snippets end up referencing r0 because we have no way of distinguishing 
the upper and the lower halves:

	(set (subreg:SI (reg:V2SI r0) 0) (reg:SI xx))
	(set (subreg:SI (reg:V2SI r0) 4) (reg:SI xx))

It was suggested that we add new RTL code to deal with this, but the 
exact semantics had not been proposed.  I'm taking this up again, and 
here is the proposed syntax:

	(vec_set_unit:SI (reg:V2SI r9) 1 (reg:SI r5))

and

	(set (reg:SI r88) (vec_get_unit:SI (reg:V2SI r9) 1))

Then, the expanders:

(define_expand "vec_set_unitv2si"
	(set (match_operand:V2SI 0)
	     (vec_set_unit:V2SI (match_operand:V2SI 1)
				(match_operand 2 immediate)
				(match_operand:SI 3)))

and...

(define_expand "vec_get_unitv2si"
   [(set (match_operand:SI 0)
	    (vec_get_unit:SI (match_operand:V2SI 1)
						 (match_operand:SI 2)))]

I think it's all pretty clear.  If no one objects as to the syntax, 
I'll start hacking away.

Aldy