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From: Richard Guenther <richard.guenther@gmail.com>
To: Richard Earnshaw <rearnsha@arm.com>
Cc: Michael Matz <matz@suse.de>,
	Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>,
	 	Mark Mitchell <mark@codesourcery.com>,
	gcc@gcc.gnu.org
Subject: Re: GCC 4.5.0 Status Report (2009-05-05)
Date: Wed, 06 May 2009 15:49:00 -0000	[thread overview]
Message-ID: <84fc9c000905060849k6ba8f575j11fa600816b5e528@mail.gmail.com> (raw)
In-Reply-To: <1241624792.5723.15.camel@pc960.cambridge.arm.com>

On Wed, May 6, 2009 at 5:46 PM, Richard Earnshaw <rearnsha@arm.com> wrote:
> On Wed, 2009-05-06 at 17:44 +0200, Michael Matz wrote:
>> Hi,
>>
>> On Wed, 6 May 2009, Ramana Radhakrishnan wrote:
>>
>> > >>> The slush that I requested last week has been lifted.  However, I
>> > >>> have asked for relative calm until the cond-optab branch has been
>> > >>> merged to mainline, which will hopefully occur on Friday, May 8th.
>> > >>
>> > >> As of this morning (UK), native bootstrap on ARM is still broken.
>> > >
>> > > Is this PR 39978?
>> >
>> > I see what's been reported at
>> > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40031#c2 on gcc55 which appears
>> > to be the same crash as what Julian's been seeing with
>> > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39929#c12.
>>
>> As written by Andrew Pinski already, you'll need a different method of
>> emitting the load of the PIC register.  The ARM backend tries to emit that
>> load as soon as it sees the PIC register being used (which is a slightly
>> odd method as it magically emits instructions at a place unrelated to the
>> instruction that currently are supposed to be emitted).
>>
>> With expand from SSA this happens earlier than before, in fact so early
>> that you don't have any basic block in RTL yet.  All are still in gimple
>> form.  That's why the emission of RTL insns after the function entry is
>> not going to work.  That's only possible if everything is transformed
>> already.
>>
>> The easiest solution would be to just make a note that you need the PIC
>> register and then, when expanding the prologue emit the necessary
>> instructions.  IMO that makes sense as PIC register setup usually is
>> something the prologue does, like all the other register setups necessary.
>>
>
> That won't work because the PIC register on ARM is a pseudo, so
> generating it during prologue generation is too late.  It needs to exist
> before data flow analysis starts on the RTL.

So you can generate it unconditionally and let DCE remove it if it turns
out not necessary?

Richard.

  reply	other threads:[~2009-05-06 15:49 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-05-05 16:25 Mark Mitchell
2009-05-06 15:06 ` Richard Earnshaw
2009-05-06 15:10   ` Mark Mitchell
2009-05-06 15:27     ` Ramana Radhakrishnan
2009-05-06 15:45       ` Michael Matz
2009-05-06 15:47         ` Richard Earnshaw
2009-05-06 15:49           ` Richard Guenther [this message]
2009-05-06 15:51             ` Richard Earnshaw
2009-05-06 15:56           ` Michael Matz
2009-05-06 15:58             ` Richard Earnshaw
2009-05-07 14:27 ` cond-optab merge delay? [was Re: GCC 4.5.0 Status Report (2009-05-05)] Paolo Bonzini
2009-05-07 18:06   ` Mark Mitchell
2009-05-08 16:55   ` Ramana Radhakrishnan

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