From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 64C2B3883035 for ; Tue, 28 Nov 2023 12:52:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 64C2B3883035 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=linux.vnet.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 64C2B3883035 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701175935; cv=none; b=fJI7PFDDnBGwv1dnWOGUoD6Wva84Smm6Rx/48NGk+EWbJQ99ZFJzFvj3PuHkEZcB1wNY1QYRuKcEC3qcIvUZI39yrx/qWKvuM3dv+BJCYXVCgcFtVF9AiGc3Uatv/cuujJ0kcKjn6B/rwHUeHQgH+leI74egNJKoJBxg9Nmtxd0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701175935; c=relaxed/simple; bh=EQ29Y4LWxSBzCFtdulvT1apzcdRV/H5eIkzbjGu6+8s=; h=DKIM-Signature:Message-ID:Date:Subject:To:From:MIME-Version; b=BoxMcc0/CsH3/RKBowz4ibVulYRP9dtN/AsbdMhNLkVd9wJViHfl/K3MKOcXQUGzlqmQuWYL+jSuOjU1pCERlJmXQyOCxRuQSdpaccLczD/sq4hLTlu0ZtfRINsSaPgk0ge/bOwSuiW3droYigwrPQC1Nxx+fsp6lyjwGLJDjM8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0353728.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3ASCjfsq013886; Tue, 28 Nov 2023 12:52:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pp1; bh=4dQq8adRWI3MNnFxuJc3r9Qp87o2OisaIzGwHND85tI=; b=rKZP9feqkTuAX/N3yabX6p41PlxGGfGf7Sog8zGxub4eDccD8u53TJvdYN9USM6ACVsR 4QzCgSsSS+JFTkF/d3G3MoSPayWwPxD+k6OCkAX8z2L6UFwYaKBy4Ob0vt+TOfXSdeZr CEw7JKTHRgTrsZMulVe2Oo8QxWM8cLBmv1mhjfUKOh6fqzk6gfzMqow/qdidLUWKHap1 HYlHQM8LvUCX65Uq+gkJm10hSomDu0PBeu2/ONni4VsaOgpz1ESAPlQ4IqkxjOo2O/+N 5G/PQ55H9mjx84kjaXyMd7skHWpmIIL1JCXSebZU81kIpGcfVArc2gLZ/qCKHVpK26r9 zQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3unfbg220a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Nov 2023 12:52:07 +0000 Received: from m0353728.ppops.net (m0353728.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3ASCjgrM013961; Tue, 28 Nov 2023 12:52:07 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3unfbg21yq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Nov 2023 12:52:07 +0000 Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3ASAXAWC018242; Tue, 28 Nov 2023 12:52:05 GMT Received: from smtprelay02.wdc07v.mail.ibm.com ([172.16.1.69]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 3ukwy1q4vf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Nov 2023 12:52:05 +0000 Received: from smtpav04.wdc07v.mail.ibm.com (smtpav04.wdc07v.mail.ibm.com [10.39.53.231]) by smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3ASCq58t21889574 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 28 Nov 2023 12:52:05 GMT Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1F47658045; Tue, 28 Nov 2023 12:52:05 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3AC0658052; Tue, 28 Nov 2023 12:52:03 +0000 (GMT) Received: from [9.61.160.101] (unknown [9.61.160.101]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTP; Tue, 28 Nov 2023 12:52:02 +0000 (GMT) Message-ID: <85f7385c-b14a-4326-88fb-80bbf9b53cc4@linux.vnet.ibm.com> Date: Tue, 28 Nov 2023 18:22:01 +0530 User-Agent: Mozilla Thunderbird Subject: Re: Discussion about arm/aarch64 testcase failures seen with patch for PR111673 Content-Language: en-US To: Richard Earnshaw , Richard Sandiford , Peter Bergner Cc: GCC Development , vmakarov@redhat.com References: <51f4b26f-1462-45c2-8106-fbfe8dc61975@linux.vnet.ibm.com> <2a2060c7-5288-422d-ba1d-dfe4306b4c3f@linux.vnet.ibm.com> <566f7575-10c1-42b7-b006-f77a631a20cb@foss.arm.com> From: Surya Kumari Jangala In-Reply-To: <566f7575-10c1-42b7-b006-f77a631a20cb@foss.arm.com> Content-Type: text/plain; charset=UTF-8 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: GyXJrtm-x-qwEDRa57-3tTCY09Flx_H5 X-Proofpoint-ORIG-GUID: OQGWpkSVuLvf2nbRvc4Ci1obk4MkZtHj Content-Transfer-Encoding: 8bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-28_12,2023-11-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311280102 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Richard, Thanks a lot for your response! Another failure reported by the Linaro CI is as follows : (Note: I am planning to send a separate mail for each failure, as this will make the discussion easy to track) FAIL: gcc.target/aarch64/sve/acle/general/cpy_1.c -march=armv8.2-a+sve -moverride=tune=none check-function-bodies dup_x0_m Expected code: ... add (x[0-9]+), x0, #?1 mov (p[0-7])\.b, p15\.b mov z0\.d, \2/m, \1 ... ret Code obtained w/o patch: addvl sp, sp, #-1 str p15, [sp] add x0, x0, 1 mov p3.b, p15.b mov z0.d, p3/m, x0 ldr p15, [sp] addvl sp, sp, #1 ret Code obtained w/ patch: addvl sp, sp, #-1 str p15, [sp] mov p3.b, p15.b add x0, x0, 1 mov z0.d, p3/m, x0 ldr p15, [sp] addvl sp, sp, #1 ret As we can see, with the patch, the following two instructions are interchanged: add x0, x0, 1 mov p3.b, p15.b I believe that this is fine and the test can be modified to allow it to pass on aarch64. Please let me know what you think. Regards, Surya On 24/11/23 4:18 pm, Richard Earnshaw wrote: > > > On 24/11/2023 08:09, Surya Kumari Jangala via Gcc wrote: >> Hi Richard, >> Ping. Please let me know if the test failure that I mentioned in the mail below can be handled by changing the expected generated code. I am not conversant with arm, and hence would appreciate your help. >> >> Regards, >> Surya >> >> On 03/11/23 4:58 pm, Surya Kumari Jangala wrote: >>> Hi Richard, >>> I had submitted a patch for review (https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631849.html) >>> regarding scaling save/restore costs of callee save registers with block >>> frequency in the IRA pass (PR111673). >>> >>> This patch has been approved by VMakarov >>> (https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632089.html). >>> >>> With this patch, we are seeing performance improvements with spec on x86 >>> (exchange: 5%, xalancbmk: 2.5%) and on Power (perlbench: 5.57%). >>> >>> I received a mail from Linaro about some failures seen in the CI pipeline with >>> this patch. I have analyzed the failures and I wish to discuss the analysis with you. >>> >>> One failure reported by the Linaro CI is: >>> >>> FAIL: gcc.target/arm/pr111235.c scan-assembler-times ldrexd\tr[0-9]+, r[0-9]+, \\[r[0-9]+\\] 2 >>> >>> The diff in the assembly between trunk and patch is: >>> >>> 93c93 >>> <       push    {r4, r5} >>> --- >>>>        push    {fp} >>> 95c95 >>> <       ldrexd  r4, r5, [r0] >>> --- >>>>        ldrexd  fp, ip, [r0] >>> 99c99 >>> <       pop     {r4, r5} >>> --- >>>>        ldr     fp, [sp], #4 >>> >>> >>> The test fails with patch because the ldrexd insn uses fp & ip registers instead >>> of r[0-9]+ >>> >>> But the code produced by patch is better because it is pushing and restoring only >>> one register (fp) instead of two registers (r4, r5). Hence, this test can be >>> modified to allow it to pass on arm. Please let me know what you think. >>> >>> If you need more information, please let me know. I will be sending separate mails >>> for the other test failures. >>> > > Thanks for looking at this. > > > The key part of this test is that the compiler generates LDREXD.  The registers used for that are pretty much irrelevant as we don't match them to any other operations within the test.  So I'd recommend just testing for the mnemonic and not for any of the operands (ie just match "ldrexd\t"). > > R. > >>> Regards, >>> Surya >>> >>> >>>