From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26443 invoked by alias); 27 Jan 2014 16:06:05 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 26430 invoked by uid 89); 27 Jan 2014 16:06:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ea0-f182.google.com Received: from mail-ea0-f182.google.com (HELO mail-ea0-f182.google.com) (209.85.215.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 27 Jan 2014 16:06:03 +0000 Received: by mail-ea0-f182.google.com with SMTP id r15so2390821ead.41 for ; Mon, 27 Jan 2014 08:06:00 -0800 (PST) X-Received: by 10.15.35.194 with SMTP id g42mr25447937eev.20.1390838759961; Mon, 27 Jan 2014 08:05:59 -0800 (PST) Received: from sandifor-thinkpad.stglab.manchester.uk.ibm.com (gbibp9ph1--blueice2n1.emea.ibm.com. [195.212.29.75]) by mx.google.com with ESMTPSA id n7sm43954608eef.5.2014.01.27.08.05.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Jan 2014 08:05:59 -0800 (PST) From: Richard Sandiford To: Paulo Matos Mail-Followup-To: Paulo Matos ,"gcc\@gcc.gnu.org" , rdsandiford@googlemail.com Cc: "gcc\@gcc.gnu.org" Subject: Re: Mode change for bswap pattern expansion In-Reply-To: <19EB96622A777C4AB91610E763265F463F12AC@SJEXCHMB14.corp.ad.broadcom.com> (Paulo Matos's message of "Mon, 27 Jan 2014 11:15:36 +0000") References: <19EB96622A777C4AB91610E763265F463F12AC@SJEXCHMB14.corp.ad.broadcom.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) Date: Mon, 27 Jan 2014 16:24:00 -0000 Message-ID: <877g9ltnoj.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2014-01/txt/msg00281.txt.bz2 Paulo Matos writes: > On a vector processor we can do a bswapsi with two instructions, by first rotating half-words (16 bits) by 8 and then rotating full words by 16. > However, this means expanding: > (set (match_operand:SI 0 "register_operand" "") > (bswap:SI (match_operand:SI 1 "register_operand" ""))) > > to: > (set (match_dup:V2HI 0) > (rotate:V2HI (match_dup:V2HI 1) > (const_int 8))) > (set (match_dup:SI 0) > (rotate:SI (match_dup:SI 0) > (const_int 16))) > > This is obviously not correct, because match_dup cannot set the mode. The point I am trying to make is that I can't find a good way to deal with the mode changes. I don't think GCC is too happy if I change the modes of the same operand from one instruction to the other right? The only other way is to emit paradoxical subregs. So something along these lines: > (set (subreg:V2HI (match_dup 0) 0) > (rotate:V2HI (subreg:V2HI (match_dup 1) 0) > (const_int 8))) > (set (match_dup 0) > (rotate:SI (match_dup 0) > (const_int 16))) It's usually better not to hard-code the subregs in the pattern. Instead you could use C code to create the subregs, e.g.: [(set (match_dup 3) (rotate:V2HI (match_dup 2) (const_int 8))) (set (match_dup 0) (rotate:SI (match_dup 4) (const_int 16)))] "" { operands[2] = gen_lowpart (V2HImode, operands[1]); operands[3] = gen_reg_rtx (V2HImode); operands[4] = gen_lowpart (SImode, operands[3]); } so that any hard regs are correctly handled. Or it might be easier to code it using emit_insn (gen_* (...))s instead. BTW, paradoxical subregs are where the outer mode is strictly larger than the inner mode. MIPS uses essentially the same sequence, except that it has a special instruction to do the first rotate (WSBH), rather than it being an instance of a general vector rotate. For MIPS we just model it as an unspec SImode operation. Maybe that would be easier here too. Thanks, Richard