From: Richard Sandiford <richard.sandiford@linaro.org>
To: Steve Ellcey <sellcey@cavium.com>
Cc: "Richard Earnshaw \(lists\)" <Richard.Earnshaw@arm.com>,
Francesco Petrogalli <Francesco.Petrogalli@arm.com>,
James Greenhalgh <James.Greenhalgh@arm.com>, "Sekhar\,
Ashwin" <Ashwin.Sekhar@cavium.com>, gcc <gcc@gcc.gnu.org>,
Marcus Shawcroft <Marcus.Shawcroft@arm.com>, nd <nd@arm.com>
Subject: Re: [Aarch64] Vector Function Application Binary Interface Specification for OpenMP
Date: Wed, 16 May 2018 21:11:00 -0000 [thread overview]
Message-ID: <87a7sznw5c.fsf@linaro.org> (raw)
In-Reply-To: <1526491802.29509.19.camel@cavium.com> (Steve Ellcey's message of "Wed, 16 May 2018 10:30:02 -0700")
Steve Ellcey <sellcey@cavium.com> writes:
> On Wed, 2018-05-16 at 17:30 +0100, Richard Earnshaw (lists) wrote:
>> On 16/05/18 17:21, Steve Ellcey wrote:
>> >
>> > It doesn't look like GCC has any existing mechanism for having different
>> > sets of caller saved/callee saved registers depending on the function
>> > attributes of the calling or called function.
>> >
>> > Changing what registers a callee function saves and restores shouldn't
>> > be too difficult since that can be done when generating the prologue
>> > and epilogue code but changing what registers a caller saves/restores
>> > when doing the call seems trickier. The macro
>> > TARGET_HARD_REGNO_CALL_PART_CLOBBERED doesn't know anything about the
>> > function being called. It returns true/false depending on just the
>> > register number and mode.
>> >
>> > Steve Ellcey
>> > sellcey@cavium.com
>> >
>>
>> Actually, we can. See, for example, the attribute((pcs)) for the ARM
>> port. I think we could probably handle this automagically for the SVE
>> vector calling convention in AArch64.
>>
>> R.
>
> Interesting, it looks like one could use aarch64_emit_call to emit
> extra use_reg / clobber_reg instructions but in this case we want to
> tell the caller that some registers are not being clobbered by the
> callee. The ARM port does not
> define TARGET_HARD_REGNO_CALL_PART_CLOBBERED and that seemed like one
> of the most problamatic issues with Aarch64. Maybe we would have to
> undefine this for aarch64 and use explicit clobbers to say what
> floating point registers / vector registers are clobbered for each
> call? I wonder how that would affect register allocation.
TARGET_HARD_REGNO_CALL_PART_CLOBBERED is the only current way
of saying that an rtl instruction preserves the low part of a
register but clobbers the high part. We would need something like
Alan H's CLOBBER_HIGH patches to do it using explicit clobbers.
Another approach would be to piggy-back on the -fipa-ra infrastructure
and record that vector PCS functions only clobber Q0-Q7. If -fipa-ra
knows that a function doesn't clobber Q8-Q15 then that should override
TARGET_HARD_REGNO_CALL_PART_CLOBBERED. (I'm not sure whether it does
in practice, but it should :-) And if it doesn't that's a bug that's
worth fixing for its own sake.)
Thanks,
Richard
next prev parent reply other threads:[~2018-05-16 21:11 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-09 21:47 Steve Ellcey
2018-05-15 18:29 ` Francesco Petrogalli
2018-05-16 16:21 ` Steve Ellcey
2018-05-16 16:30 ` Richard Earnshaw (lists)
2018-05-16 17:30 ` Steve Ellcey
2018-05-16 21:11 ` Richard Sandiford [this message]
2018-05-24 17:50 ` Steve Ellcey
2018-05-26 10:09 ` Richard Sandiford
2018-05-26 22:13 ` Segher Boessenkool
2018-05-27 15:59 ` Jeff Law
2018-05-29 10:06 ` Richard Sandiford
2018-05-31 10:39 ` Alan Hayward
2018-06-12 3:11 ` Jeff Law
2018-06-11 23:06 ` Jeff Law
2018-07-02 18:16 ` Francesco Petrogalli
-- strict thread matches above, loose matches on Subject: below --
2017-03-15 9:50 Sekhar, Ashwin
2017-03-17 14:02 ` James Greenhalgh
2017-03-20 4:30 ` Sekhar, Ashwin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87a7sznw5c.fsf@linaro.org \
--to=richard.sandiford@linaro.org \
--cc=Ashwin.Sekhar@cavium.com \
--cc=Francesco.Petrogalli@arm.com \
--cc=James.Greenhalgh@arm.com \
--cc=Marcus.Shawcroft@arm.com \
--cc=Richard.Earnshaw@arm.com \
--cc=gcc@gcc.gnu.org \
--cc=nd@arm.com \
--cc=sellcey@cavium.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).