From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa2.mentor.iphmx.com (esa2.mentor.iphmx.com [68.232.141.98]) by sourceware.org (Postfix) with ESMTPS id 47A0C3858C3B for ; Wed, 15 Sep 2021 11:20:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 47A0C3858C3B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: 2BpdmiWYZLYhUars/YmCTSWbtAbLL8dHjSFn8TqmDA5AMsruXs5Su28QS3H6YWFkLc0CNR93nc RTRXYIdFSrAT340zUptzFT3/5Pv6g27UXbvvzG08pVuVPKtsZAwNof/FNr66kuZjLcVzRTf89w R6QU6GjNjxYPiwQbAMuxIDKBV90qjfaRa6Rd9O4KrMCa7mh9TfJrCEWMQZfU67+x5VfIwe25ic SxLHgbzgYD2PxlCB6iNvHFu3GOx6vaGkVre51VrgIkQalUWCZXc4bt2heMxkMNLWBt52JJkdPQ SIb9OqxzXXeuKY7zNBpIOCp4 X-IronPort-AV: E=Sophos;i="5.85,295,1624348800"; d="scan'208";a="65885512" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa2.mentor.iphmx.com with ESMTP; 15 Sep 2021 03:20:03 -0800 IronPort-SDR: hgVURKnoKsErIxZ+waTQ46eS7BViYcu7BUksHEGMpbCAn/RNWc/hPqYmTlM4/gHVRNg+r+nNck qYwMr43PgHYZ6P0i6XM5a1X/s1bv5lkseOotm8o1CySjoVdTXrgoH9x+OObDVJn8sxT5WTd61r 6IN6lirSFNUTJVhACkLbjdkHUhtboaOs9FKAfYoR45T7pGZAjTx55hkVyDwdS6RC/IRVfmfos3 gvWl3lcqgmIuNaY3w4gyNQha1EjnMm4PNoqw7n73Xi1h5jyYcZ4PlTTpB2HmH8C/EhzHAHxoQy 8fI= From: Thomas Schwinge To: Hongtao Liu CC: , Jakub Jelinek , Tobias Burnus , Kirill Yukhin , Richard Biener Subject: RE: GCC/OpenMP offloading for Intel GPUs? In-Reply-To: References: <87v933nlhn.fsf@dem-tschwing-1.ger.mentorg.com> User-Agent: Notmuch/0.29.3+94~g74c3f1b (https://notmuchmail.org) Emacs/27.1 (x86_64-pc-linux-gnu) Date: Wed, 15 Sep 2021 13:19:52 +0200 Message-ID: <87czpat7af.fsf@euler.schwinge.homeip.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-02.mgc.mentorg.com (139.181.222.2) To svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Sep 2021 11:20:06 -0000 Hi! On 2021-09-15T02:00:33+0000, "Liu, Hongtao via Gcc" wrote= : > I got some feedback from my colleague Thanks for reaching out to them. > ----------------- > What we need from GCC > > 1. generate SPIR-V > 2. offload bundler to create FAT object > -------------- > > If the answer is yes for both, they can hook it up with libomptarget libr= ary and our IGC back-end. OK, I didn't remember Intel's use of SPIR-V as intermediate representation (but that's certainly good!), and leaving aside the technical/implementation issues (regarding libomptarget etc. use, as brought up by Jakub), the question then is: are Intel planning to do that work (themselves, like for Intel MIC offloading back then), or interested in hiring someone to do it, or not? Gr=C3=BC=C3=9Fe Thomas >>-----Original Message----- >>From: Thomas Schwinge >>Sent: Wednesday, September 15, 2021 12:57 AM >>To: gcc@gcc.gnu.org >>Cc: Jakub Jelinek ; Tobias Burnus >>; Kirill Yukhin ; Liu, >>Hongtao >>Subject: GCC/OpenMP offloading for Intel GPUs? >> >>Hi! >> >>I've had a person ask about GCC/OpenMP offloading for Intel GPUs (the new >>ones, not MIC, obviously), to complement the existing support for Nvidia = and >>AMD GPUs. Is there any statement other than "ought to be doable; someone >>needs to contribute the work"? >> >> >>Gr=C3=BC=C3=9Fe >> Thomas >>----------------- >>Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstra=C3=9Fe 2= 01, >>80634 M=C3=BCnchen; Gesellschaft mit beschr=C3=A4nkter Haftung; Gesch=C3= =A4ftsf=C3=BChrer: >>Thomas Heurung, Frank Th=C3=BCrauf; Sitz der Gesellschaft: M=C3=BCnchen; >>Registergericht M=C3=BCnchen, HRB 106955 ----------------- Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstra=C3=9Fe 201= , 80634 M=C3=BCnchen; Gesellschaft mit beschr=C3=A4nkter Haftung; Gesch=C3= =A4ftsf=C3=BChrer: Thomas Heurung, Frank Th=C3=BCrauf; Sitz der Gesellschaf= t: M=C3=BCnchen; Registergericht M=C3=BCnchen, HRB 106955