From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29875 invoked by alias); 7 Jan 2003 12:06:22 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 29865 invoked from network); 7 Jan 2003 12:06:20 -0000 Received: from unknown (HELO freon) (80.72.64.67) by 209.249.29.67 with SMTP; 7 Jan 2003 12:06:20 -0000 Received: by freon (Postfix, from userid 1000) id F0D99500005; Tue, 7 Jan 2003 14:06:04 +0200 (EET) To: dewar@gnat.com (Robert Dewar) Cc: ja_walker@earthlink.net, lord@emf.net, mszick@goquest.com, gcc@gcc.gnu.org Subject: Re: An unusual Performance approach using Synthetic registers References: <20030107115052.04121F28F4@nile.gnat.com> X-No-CC: Reply to lists, not to me. From: Momchil Velikov In-Reply-To: <20030107115052.04121F28F4@nile.gnat.com> Date: Tue, 07 Jan 2003 12:10:00 -0000 Message-ID: <87el7pqi4z.fsf@fadata.bg> User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2003-01/txt/msg00344.txt.bz2 >>>>> "Robert" == Robert Dewar writes: >> I am pretty familiar with the x86 instruction set, but I clearly recall that >> I have never seen anything like this. Is there such a thing in the x86 >> instruction set, and if so, what is it called? Is it perhaps one of the >> testing instructions? Robert> There is no prefetch instruction as such on the x86, but of course any Robert> access acts as a prefetch in practice. There is, actually, Opcode Instruction Description 0F 18 /1 PREFETCHT0 m8 Move data from m8 closer to the processor using T0 hint. 0F 18 /2 PREFETCHT1 m8 Move data from m8 closer to the processor using T1 hint. 0F 18 /3 PREFETCHT2 m8 Move data from m8 closer to the processor using T2 hint. 0F 18 /0 PREFETCHNTA m8 Move data from m8 closer to the processor using NTA hint. Description Fetches the line of data from memory that contains the byte specified with the source operand to a location in the cache hierarchy specified by a locality hint: * T0 (temporal data) prefetch data into all levels of the cache hierarchy. Pentium III processor 1st- or 2nd-level cache. Pentium 4 and Intel Xeon processor 2nd-level cache. * T1 (temporal data with respect to first level cache) prefetch data into level 2 cache and higher. Pentium III processor 2nd-level cache. Pentium 4 and Intel Xeon processor 2nd-level cache. * T2 (temporal data with respect to second level cache) prefetch data into level 2 cache and higher. Pentium III processor 2nd-level cache. Pentium 4 and Intel Xeon processor 2nd-level cache. * NTA (non-temporal data with respect to all cache levels) prefetch data into non-temporal cache structure and into a location close to the processor, minimizing cache pollution. Pentium III processor 1st-level cache Pentium 4 and Intel Xeon processor 2nd-level cache ~velco