From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1071 invoked by alias); 9 Feb 2014 12:27:54 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 1054 invoked by uid 89); 9 Feb 2014 12:27:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f170.google.com Received: from mail-wi0-f170.google.com (HELO mail-wi0-f170.google.com) (209.85.212.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Sun, 09 Feb 2014 12:27:50 +0000 Received: by mail-wi0-f170.google.com with SMTP id hi5so1982793wib.3 for ; Sun, 09 Feb 2014 04:27:47 -0800 (PST) X-Received: by 10.180.37.178 with SMTP id z18mr6731138wij.46.1391948867766; Sun, 09 Feb 2014 04:27:47 -0800 (PST) Received: from localhost ([2.28.234.162]) by mx.google.com with ESMTPSA id gt6sm26345623wib.8.2014.02.09.04.27.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 09 Feb 2014 04:27:47 -0800 (PST) From: Richard Sandiford To: Umesh Kalappa Mail-Followup-To: Umesh Kalappa ,"gcc\@gcc.gnu.org" , rdsandiford@googlemail.com Cc: "gcc\@gcc.gnu.org" Subject: Re: type promotion References: Date: Sun, 09 Feb 2014 12:27:00 -0000 In-Reply-To: (Umesh Kalappa's message of "Wed, 29 Jan 2014 15:20:08 +0530") Message-ID: <87txc84gjh.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2014-02/txt/msg00107.txt.bz2 Sorry for the late answer. Umesh Kalappa writes: > Was porting gcc 4.8.1 to the private target which has 8 bit regs and > can be used as pair for 16bit like AB ,CD but not BC or AD. > > I was stuck in the type promotion like > > int i; > unsigned char c; > > int test () > { > i =3Dc; > } > > defined the zero_extendqihi2 pattern for the above c construct like > > (define_expand zero_extendqihi2 > [(set (operand:hi 0 "" """) > (zero_extend:hi (operand:qi 1)))] > "" > if(!reload_completed) > { > if(operands[1] !=3D REG) > operands[1]=3D force_reg(QI,operands[1]); > > /* Here i need to enforce gcc to use the next consective paired reg > like B if operands[1] is in A reg or D if operands[1] is in C */ > } > ) > > How do i module the above reguirement in the backend ? You might have already solved this by now, but this kind of restriction is usually modelled via HARD_REGNO_MODE_OK. A and C would be =E2=80=9COK= =E2=80=9D for HImode but B and D wouldn't. Did you single out zero_extend because the QImode input also needs to follow the same rules? If so, the way to model that depends on the restriction. If the QImode input to the zero_extend must be in the low 8 bits of the output register then you can use matching constraints like "0" for the input operand. (It's OK to match operands of different sizes like this.) If instead the QImode input is independent of the HImode output but can only go in certain registers (perhaps just A or C, for example) then you can define a register class that just includes those registers. You'd then need an associated define_register_constraint. Thanks, Richard