From: Zack Weinberg <zack@codesourcery.com>
To: Steve Ellcey <sje@cup.hp.com>
Cc: gcc@gcc.gnu.org
Subject: Re: IA64 floating point division question
Date: Wed, 01 Sep 2004 00:10:00 -0000 [thread overview]
Message-ID: <87zn4a26i7.fsf@codesourcery.com> (raw)
In-Reply-To: <200408312358.QAA26610@hpsje.cup.hp.com> (Steve Ellcey's message of "Tue, 31 Aug 2004 16:58:02 -0700 (PDT)")
Steve Ellcey <sje@cup.hp.com> writes:
>> I'm fairly sure that your problem is with the "*recip_approx"
>> instruction, which is what is supposed to match this pattern. The
>> catch is, it *only* allows XFmode operands, whereas you're trying to
>> feed it SFmode.
>
> No, I created some new versions of *recip_approx that "generate" SFmode
> or DFmode (as well as some new _alts instructions) so that I can refer
> to each register in only one mode. My new *recip_approx_sf instruction
> is:
>
> (define_insn "*recip_approx_sf"
> [(set (match_operand:SF 0 "fr_register_operand" "=f")
> (div:SF (const_int 1)
> (match_operand:SF 3 "fr_register_operand" "f")))
> (set (match_operand:BI 1 "register_operand" "=c")
> (unspec:BI [(match_operand:SF 2 "fr_register_operand" "f")
> (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
> (use (match_operand:SI 4 "const_int_operand" ""))]
> ""
> "frcpa.s%4 %0, %1 = %2, %3"
> [(set_attr "itanium_class" "fmisc")
> (set_attr "predicable" "no")])
Odd; that certainly ought to match the pattern you showed. I have no
idea why it wouldn't.
zw
next parent reply other threads:[~2004-09-01 0:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200408312358.QAA26610@hpsje.cup.hp.com>
2004-09-01 0:10 ` Zack Weinberg [this message]
2004-08-31 23:20 Steve Ellcey
2004-08-31 23:58 ` Zack Weinberg
2004-09-01 12:25 ` Joern Rennecke
2004-09-01 12:28 ` Joern Rennecke
2004-09-01 17:51 ` Steve Ellcey
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