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From: Francesco Petrogalli <Francesco.Petrogalli@arm.com>
To: "sellcey@cavium.com" <sellcey@cavium.com>
Cc: James Greenhalgh <James.Greenhalgh@arm.com>,
	"Sekhar, Ashwin"	<Ashwin.Sekhar@cavium.com>,
	gcc <gcc@gcc.gnu.org>,
	Richard Earnshaw	<Richard.Earnshaw@arm.com>,
	Marcus Shawcroft <Marcus.Shawcroft@arm.com>, nd	<nd@arm.com>
Subject: Re: [Aarch64] Vector Function Application Binary Interface Specification for OpenMP
Date: Mon, 02 Jul 2018 18:16:00 -0000	[thread overview]
Message-ID: <9BB064BC-BB81-4D9F-B2EE-68CA08F9B222@arm.com> (raw)
In-Reply-To: <1526487700.29509.6.camel@cavium.com>

Dear all,

I just want to let you know that we just published the final version of the Vector Function ABI specification. The call-clobbered and call-preserved lists of register has been updated (see section 2.1) .

The document is located at the same address:

https://developer.arm.com/products/software-development-tools/hpc/arm-compiler-for-hpc/vector-function-abi

Kind regards,

Francesco

> On May 16, 2018, at 11:21 AM, Steve Ellcey <sellcey@cavium.com> wrote:
> 
> On Tue, 2018-05-15 at 18:29 +0000, Francesco Petrogalli wrote:
> 
>> Hi Steve,
>> 
>> I am happy to let you know that the Vector Function ABI for AArch64
>> is now public and available via the link at [1].
>> 
>> Don’t hesitate to contact me in case you have any questions.
>> 
>> Kind regards,
>> 
>> Francesco
>> 
>> [1] https://developer.arm.com/products/software-development-tools/hpc
>> /arm-compiler-for-hpc/vector-function-abi
>> 
>>> 
>>> Steve Ellcey
>>> sellcey@cavium.com
> 
> Thanks for publishing this Francesco, it looks like the main issue for
> GCC is that the Vector Function ABI has different caller saved / callee
> saved register conventions than the standard ARM calling convention.
> 
> If I understand things correctly, in the standard calling convention
> the callee will only save the bottom 64 bits of V8-V15 and so the
> caller needs to save those registers if it is using the top half.  In
> the Vector calling convention the callee will save all 128 bits of
> these registers (and possibly more registers) so the caller does not
> have to save these registers at all, even if it is using all 128 bits
> of them.
> 
> It doesn't look like GCC has any existing mechanism for having different
> sets of caller saved/callee saved registers depending on the function
> attributes of the calling or called function.
> 
> Changing what registers a callee function saves and restores shouldn't
> be too difficult since that can be done when generating the prologue
> and epilogue code but changing what registers a caller saves/restores
> when doing the call seems trickier.  The macro
> TARGET_HARD_REGNO_CALL_PART_CLOBBERED doesn't know anything about the
> function being called.  It returns true/false depending on just the
> register number and mode.
> 
> Steve Ellcey
> sellcey@cavium.com


  parent reply	other threads:[~2018-07-02 18:16 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-09 21:47 Steve Ellcey
2018-05-15 18:29 ` Francesco Petrogalli
2018-05-16 16:21   ` Steve Ellcey
2018-05-16 16:30     ` Richard Earnshaw (lists)
2018-05-16 17:30       ` Steve Ellcey
2018-05-16 21:11         ` Richard Sandiford
2018-05-24 17:50           ` Steve Ellcey
2018-05-26 10:09             ` Richard Sandiford
2018-05-26 22:13               ` Segher Boessenkool
2018-05-27 15:59               ` Jeff Law
2018-05-29 10:06                 ` Richard Sandiford
2018-05-31 10:39                   ` Alan Hayward
2018-06-12  3:11                     ` Jeff Law
2018-06-11 23:06                   ` Jeff Law
2018-07-02 18:16     ` Francesco Petrogalli [this message]
  -- strict thread matches above, loose matches on Subject: below --
2017-03-15  9:50 Sekhar, Ashwin
2017-03-17 14:02 ` James Greenhalgh
2017-03-20  4:30   ` Sekhar, Ashwin

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