Length-Changing Prefixes problem with the x86 Backend

Length-Changing Prefixes problem with the x86 Backend

[Nadav]

Hello,

I came across a problem with the x86 backend of gcc (3.3 - 4.1).  When
I compile code which access a lookup table of size 65536, gcc
generates code which uses 16bit opcodes.

The intel architecture optimization guide warns that 16bit opcodes
should be avoided whenever possible due to Length-Changing Prefixes
(LCP).  The recommendation is: ""If imm16 is needed, load equivalent
imm32 into a register and use the word value in the register instead.
""

I would expect gcc to use a 32bits register and mask it, if needed.
Even when I use 32bits registers and mask them ( & 0xFFFF), gcc
detects correctly that my variable is effectively only 16bits and it
generates 16bits code.
I modified the generated assembly to use 32bit registers and it ran much faster.

--
Cheers,
Nadav

Re: Length-Changing Prefixes problem with the x86 Backend

[Uros Bizjak]

On Wed, Jun 25, 2008 at 11:11 PM, Nadav <nadav256@gmail.com> wrote:

> I came across a problem with the x86 backend of gcc (3.3 - 4.1).  When I
> compile code which access a lookup table of size 65536, gcc generates code
> which uses 16bit opcodes.
>
> The intel architecture optimization guide warns that 16bit opcodes should be
> avoided whenever possible due to Length-Changing Prefixes (LCP).  The
> recommendation is: ""If imm16 is needed, load equivalent imm32 into a
> register and use the word value in the register instead. ""
>
> I would expect gcc to use a 32bits register and mask it, if needed.
> Even when I use 32bits registers and mask them ( & 0xFFFF), gcc detects
> correctly that my variable is effectively only 16bits and it generates
> 16bits code.
> I modified the generated assembly to use 32bit registers and it ran much
> faster.

Please file a bugreport following instructions at
http://gcc.gnu.org/bugs.html. Please also add a runtime test that can
be used to analyze the problem.

Thanks,
Uros.

Re: Length-Changing Prefixes problem with the x86 Backend

[Agner Fog]

On Thu, 26 Jun 2008 Uros wrote:

 >Please also add a runtime test that can be used to analyze the problem.

I am a temporary guest on the gcc mailing list and I haven't seen your 
mail before. In case your problem hasn't been solved yet, I can inform 
you that I have a disassembler which puts comments into the disassembly 
file in case of length-changing prefixes and other sub-optimal or 
illegal instruction codes. Just compile with -c to get an object file 
and run it on the disassembler:
objconv -fasm yourfile.o yourfile.asm

It supports all x86 instruction sets up to SSE4.2 and SSE5 (but not AVX 
and FMA yet). It may be useful for testing other compiler features as 
well, such as support for new instruction sets.

Get it from www.agner.org/optimize/objconv.zip
This is a cross-platform multi-purpose tool. The assembly output is in 
MASM format, not AT&T. Use .intel_syntax noprefix in case you want to 
assemble the disassembly on GAS.